Showing results 1 to 4 of 4
| Title | Author(s) | Issue Date | Views | |
|---|---|---|---|---|
Configurable Architecture for Double/Two-Parallel Single Precision Floating Point Division Proceeding/Conference:IEEE Computer Society Annual Symposium on VLSI (ISVLSI) | 2014 | 51 | ||
Configurable Architectures For Multi-mode Floating Point Adders Journal:IEEE Transactions On Circuits And Systems I: Regular Papers | 2015 | 42 | ||
Series Expansion based Efficient Architectures for Double Precision Floating Point Division Journal:Circuits, Systems, and Signal Processing | 2014 | 50 | ||
Unified Architecture for Double/Two-Parallel Single Precision Floating Point Adder Journal:IEEE Transactions on Circuits and Systems II: Express Briefs | 2014 |