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Article: Configurable Architectures For Multi-mode Floating Point Adders

TitleConfigurable Architectures For Multi-mode Floating Point Adders
Authors
Issue Date2015
Citation
IEEE Transactions On Circuits And Systems I: Regular Papers, 2015, v. 62, p. 2079-2090 How to Cite?
Persistent Identifierhttp://hdl.handle.net/10722/214166
ISI Accession Number ID

 

DC FieldValueLanguage
dc.contributor.authorJaiswal, MK-
dc.contributor.authorBogaraju, SV-
dc.contributor.authorSo, HKH-
dc.contributor.authorBalakrishnan, M-
dc.contributor.authorPaul, K-
dc.contributor.authorCheung, RCC-
dc.date.accessioned2015-08-21T10:51:32Z-
dc.date.available2015-08-21T10:51:32Z-
dc.date.issued2015-
dc.identifier.citationIEEE Transactions On Circuits And Systems I: Regular Papers, 2015, v. 62, p. 2079-2090-
dc.identifier.urihttp://hdl.handle.net/10722/214166-
dc.languageeng-
dc.relation.ispartofIEEE Transactions On Circuits And Systems I: Regular Papers-
dc.titleConfigurable Architectures For Multi-mode Floating Point Adders-
dc.typeArticle-
dc.identifier.emailJaiswal, MK: manishkj@hku.hk-
dc.identifier.emailBogaraju, SV: varma@hku.hk-
dc.identifier.emailSo, HKH: skhay@hkucc.hku.hk-
dc.identifier.authoritySo, HKH=rp00169-
dc.description.naturelink_to_subscribed_fulltext-
dc.identifier.doi10.1109/TCSI.2015.2452351-
dc.identifier.hkuros249063-
dc.identifier.volume62-
dc.identifier.spage2079-
dc.identifier.epage2090-
dc.identifier.isiWOS:000358616100020-

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