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Conference Paper: On minimizing feedback overhead for two-stage switches

TitleOn minimizing feedback overhead for two-stage switches
Authors
Issue Date2006
PublisherIEEE.
Citation
Globecom - Ieee Global Telecommunications Conference, 2006 How to Cite?
AbstractA novel feedback-based two-stage switch architecture is presented in [1] for solving the packet mis-sequencing problem in designing two-stage switches. With this architecture, each middle-stage port j piggybacks an N-bit VOQ occupancy vector to an output port k in each time slot. As output k and input k reside on the same line-card, input k schedules a packet for sending in the next time slot based on the N-bit feedback. In this paper, we focus on designing efficient packet scheduling algorithms for cutting down the number of feedback bits required while minimizing the negative impact to switch performance. The basic idea is to partition N VOQs at a middle-stage port into M non-overlapped sets. In each time slot, only the queue occupancies of selected sets are sent. By exploiting the otherwise wasted bandwidth in the first-stage switch, each input port is also allowed to piggyback its VOQ status to middle-stage ports. This allows each middle-stage port to intelligently select the sets of VOQs for feedback. Extensive simulation results show that among our proposed scheduling algorithms, the Set-feedback scheduler provides the best performance under various traffic conditions. © 2006 IEEE.
Persistent Identifierhttp://hdl.handle.net/10722/99707
References

 

DC FieldValueLanguage
dc.contributor.authorHu, Ben_HK
dc.contributor.authorYeung, KLen_HK
dc.contributor.authorLiu, NHen_HK
dc.date.accessioned2010-09-25T18:41:06Z-
dc.date.available2010-09-25T18:41:06Z-
dc.date.issued2006en_HK
dc.identifier.citationGlobecom - Ieee Global Telecommunications Conference, 2006en_HK
dc.identifier.urihttp://hdl.handle.net/10722/99707-
dc.description.abstractA novel feedback-based two-stage switch architecture is presented in [1] for solving the packet mis-sequencing problem in designing two-stage switches. With this architecture, each middle-stage port j piggybacks an N-bit VOQ occupancy vector to an output port k in each time slot. As output k and input k reside on the same line-card, input k schedules a packet for sending in the next time slot based on the N-bit feedback. In this paper, we focus on designing efficient packet scheduling algorithms for cutting down the number of feedback bits required while minimizing the negative impact to switch performance. The basic idea is to partition N VOQs at a middle-stage port into M non-overlapped sets. In each time slot, only the queue occupancies of selected sets are sent. By exploiting the otherwise wasted bandwidth in the first-stage switch, each input port is also allowed to piggyback its VOQ status to middle-stage ports. This allows each middle-stage port to intelligently select the sets of VOQs for feedback. Extensive simulation results show that among our proposed scheduling algorithms, the Set-feedback scheduler provides the best performance under various traffic conditions. © 2006 IEEE.en_HK
dc.languageengen_HK
dc.publisherIEEE.en_HK
dc.relation.ispartofGLOBECOM - IEEE Global Telecommunications Conferenceen_HK
dc.titleOn minimizing feedback overhead for two-stage switchesen_HK
dc.typeConference_Paperen_HK
dc.identifier.emailYeung, KL:kyeung@eee.hku.hken_HK
dc.identifier.authorityYeung, KL=rp00204en_HK
dc.description.naturelink_to_subscribed_fulltext-
dc.identifier.doi10.1109/GLOCOM.2006.356en_HK
dc.identifier.scopuseid_2-s2.0-50949098129en_HK
dc.identifier.hkuros133924en_HK
dc.relation.referenceshttp://www.scopus.com/mlt/select.url?eid=2-s2.0-50949098129&selection=ref&src=s&origin=recordpageen_HK
dc.identifier.scopusauthoridHu, B=36617158500en_HK
dc.identifier.scopusauthoridYeung, KL=7202424908en_HK
dc.identifier.scopusauthoridLiu, NH=7402430988en_HK

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