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Conference Paper: ASIC design and verification in an FPGA environment

TitleASIC design and verification in an FPGA environment
Authors
Issue Date2008
PublisherIEEE.
Citation
Proceedings Of The Custom Integrated Circuits Conference, 2008, p. 737-740 How to Cite?
AbstractA unified algorithm-architecture-circuit co-design environment for dedicated signal processing hardware is presented. The approach is based on a single design description in the graphical Matlab/Simulink environment that is used for FPGA emulation, ASIC design, verification and chip testing. This unified description enables system designer with a visibility through several layers of design hierarchy down to circuit level to select the optimal architecture. The tool flow propagates up circuit-level performance and power estimates to rapidly evaluate architecture-level tradeoffs. The common Simulink design description minimizes errors in translation of the design between different descriptions, and eases the verification burden. The FPGA used for emulation can be used as a low-cost tool for testing of the fabricated ASIC. The approach is demonstrated on an ASIC for 4×4 MIMO signal processing. © 2007 IEEE.
Persistent Identifierhttp://hdl.handle.net/10722/99666
ISSN
References

 

DC FieldValueLanguage
dc.contributor.authorMarkovic, Den_HK
dc.contributor.authorChang, Cen_HK
dc.contributor.authorRichards, Ben_HK
dc.contributor.authorSo, Hen_HK
dc.contributor.authorNikolic, Ben_HK
dc.contributor.authorBrodersen, RWen_HK
dc.date.accessioned2010-09-25T18:39:30Z-
dc.date.available2010-09-25T18:39:30Z-
dc.date.issued2008en_HK
dc.identifier.citationProceedings Of The Custom Integrated Circuits Conference, 2008, p. 737-740en_HK
dc.identifier.issn0886-5930en_HK
dc.identifier.urihttp://hdl.handle.net/10722/99666-
dc.description.abstractA unified algorithm-architecture-circuit co-design environment for dedicated signal processing hardware is presented. The approach is based on a single design description in the graphical Matlab/Simulink environment that is used for FPGA emulation, ASIC design, verification and chip testing. This unified description enables system designer with a visibility through several layers of design hierarchy down to circuit level to select the optimal architecture. The tool flow propagates up circuit-level performance and power estimates to rapidly evaluate architecture-level tradeoffs. The common Simulink design description minimizes errors in translation of the design between different descriptions, and eases the verification burden. The FPGA used for emulation can be used as a low-cost tool for testing of the fabricated ASIC. The approach is demonstrated on an ASIC for 4×4 MIMO signal processing. © 2007 IEEE.en_HK
dc.languageengen_HK
dc.publisherIEEE.en_HK
dc.relation.ispartofProceedings of the Custom Integrated Circuits Conferenceen_HK
dc.titleASIC design and verification in an FPGA environmenten_HK
dc.typeConference_Paperen_HK
dc.identifier.emailSo, H:hso@eee.hku.hken_HK
dc.identifier.authoritySo, H=rp00169en_HK
dc.description.naturelink_to_subscribed_fulltext-
dc.identifier.doi10.1109/CICC.2007.4405836en_HK
dc.identifier.scopuseid_2-s2.0-39549122625en_HK
dc.identifier.hkuros147618en_HK
dc.relation.referenceshttp://www.scopus.com/mlt/select.url?eid=2-s2.0-39549122625&selection=ref&src=s&origin=recordpageen_HK
dc.identifier.spage737en_HK
dc.identifier.epage740en_HK
dc.identifier.scopusauthoridMarkovic, D=7004487131en_HK
dc.identifier.scopusauthoridChang, C=8343776600en_HK
dc.identifier.scopusauthoridRichards, B=7202100326en_HK
dc.identifier.scopusauthoridSo, H=10738896800en_HK
dc.identifier.scopusauthoridNikolic, B=7006055356en_HK
dc.identifier.scopusauthoridBrodersen, RW=7102134856en_HK

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