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Conference Paper: Design and optimization of highly linear CMOS low noise amplifiers via geometric programming

TitleDesign and optimization of highly linear CMOS low noise amplifiers via geometric programming
Authors
So, WKCheung, WTLiu, YKwan, HKWong, N
Issue Date2007
Citation
Asicon 2007 - 2007 7Th International Conference On Asic Proceeding, 2007, p. 423-426 How to Cite?
DOI: http://dx.doi.org/10.1109/ICASIC.2007.4415657
AbstractLinearity is an important measurement for the performance of a CMOS low noise amplifier (LNA). The high computational cost required in the linearity simulation, however, constitutes a major bottleneck in the design verification stage. In this paper, we develop a novel and systematic Geometric Programming (GP)-based approach for the optimized design of a highly linear CMOS LNA, subject to the minimization of the noise factor. Experiments confirm the remarkable efficacy and accuracy of the proposed design flow against traditional simulators. © 2007 IEEE.
Persistent Identifierhttp://hdl.handle.net/10722/99339
References
References in Scopus

 

DC FieldValueLanguage
dc.contributor.authorSo, WKen_HK
dc.contributor.authorCheung, WTen_HK
dc.contributor.authorLiu, Yen_HK
dc.contributor.authorKwan, HKen_HK
dc.contributor.authorWong, Nen_HK
dc.date.accessioned2010-09-25T18:25:48Z-
dc.date.available2010-09-25T18:25:48Z-
dc.date.issued2007en_HK
dc.identifier.citationAsicon 2007 - 2007 7Th International Conference On Asic Proceeding, 2007, p. 423-426en_HK
dc.identifier.urihttp://hdl.handle.net/10722/99339-
dc.description.abstractLinearity is an important measurement for the performance of a CMOS low noise amplifier (LNA). The high computational cost required in the linearity simulation, however, constitutes a major bottleneck in the design verification stage. In this paper, we develop a novel and systematic Geometric Programming (GP)-based approach for the optimized design of a highly linear CMOS LNA, subject to the minimization of the noise factor. Experiments confirm the remarkable efficacy and accuracy of the proposed design flow against traditional simulators. © 2007 IEEE.en_HK
dc.languageengen_HK
dc.relation.ispartofASICON 2007 - 2007 7th International Conference on ASIC Proceedingen_HK
dc.titleDesign and optimization of highly linear CMOS low noise amplifiers via geometric programmingen_HK
dc.typeConference_Paperen_HK
dc.identifier.emailWong, N:nwong@eee.hku.hken_HK
dc.identifier.authorityWong, N=rp00190en_HK
dc.description.naturelink_to_subscribed_fulltext-
dc.identifier.doi10.1109/ICASIC.2007.4415657en_HK
dc.identifier.scopuseid_2-s2.0-48349108866en_HK
dc.identifier.hkuros133568en_HK
dc.relation.referenceshttp://www.scopus.com/mlt/select.url?eid=2-s2.0-48349108866&selection=ref&src=s&origin=recordpageen_HK
dc.identifier.spage423en_HK
dc.identifier.epage426en_HK
dc.identifier.scopusauthoridSo, WK=36849240400en_HK
dc.identifier.scopusauthoridCheung, WT=24376286000en_HK
dc.identifier.scopusauthoridLiu, Y=24483708200en_HK
dc.identifier.scopusauthoridKwan, HK=21934115800en_HK
dc.identifier.scopusauthoridWong, N=35235551600en_HK

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