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Conference Paper: Reducing dynamic power consumption in FPGAs using precomputation

TitleReducing dynamic power consumption in FPGAs using precomputation
Authors
KeywordsCommercial-off-the-shelf
Design considerations
Dynamic Power
Dynamic power consumption
FPGA architectures
Issue Date2009
PublisherIEEE Computer Society. The Journal's web site is located at http://ieeexplore.ieee.org/xpl/conhome.jsp?punumber=1000290
Citation
The 2009 International Conference on Field-Programmable Technology (FPT 2009), Sydney, Australia, 9-11 December 2009. In Conference Proceedings, 2009, p. 407-410 How to Cite?
AbstractThis paper studies the effectiveness of employing precomputation in reducing dynamic power consumption in commercial off-the-shelf (COTS) FPGAs. Precomputation is a high-level logic optimization technique that lowers power consumption of a design by disabling part of the circuit based on a few relatively simple precomputation conditions. With careful design considerations, the increased logic utilization and its associated power consumption can be justified by the power saving resulted from disabling a much larger part of the design. This fundamental trade-off benefits particularly well from the tile-based structures of modern FPGAs that consist of large number of redundant logic cells. Using the design of a comparator as an example, we study the trade-offs and unique opportunities provided by modern FPGA architectures in employing precomputation as a technique to reduce dynamic power consumption. In our example, 83% of dynamic power from logic, or 43.1% of total dynamic power including routing is reduced with negligible increase in resource consumption. © 2009 IEEE.
Persistent Identifierhttp://hdl.handle.net/10722/99016
ISBN
References

 

DC FieldValueLanguage
dc.contributor.authorTsang, CCen_HK
dc.contributor.authorSo, HKHen_HK
dc.date.accessioned2010-09-25T18:12:23Z-
dc.date.available2010-09-25T18:12:23Z-
dc.date.issued2009en_HK
dc.identifier.citationThe 2009 International Conference on Field-Programmable Technology (FPT 2009), Sydney, Australia, 9-11 December 2009. In Conference Proceedings, 2009, p. 407-410en_HK
dc.identifier.isbn978-1-4244-4377-2-
dc.identifier.urihttp://hdl.handle.net/10722/99016-
dc.description.abstractThis paper studies the effectiveness of employing precomputation in reducing dynamic power consumption in commercial off-the-shelf (COTS) FPGAs. Precomputation is a high-level logic optimization technique that lowers power consumption of a design by disabling part of the circuit based on a few relatively simple precomputation conditions. With careful design considerations, the increased logic utilization and its associated power consumption can be justified by the power saving resulted from disabling a much larger part of the design. This fundamental trade-off benefits particularly well from the tile-based structures of modern FPGAs that consist of large number of redundant logic cells. Using the design of a comparator as an example, we study the trade-offs and unique opportunities provided by modern FPGA architectures in employing precomputation as a technique to reduce dynamic power consumption. In our example, 83% of dynamic power from logic, or 43.1% of total dynamic power including routing is reduced with negligible increase in resource consumption. © 2009 IEEE.en_HK
dc.languageengen_HK
dc.publisherIEEE Computer Society. The Journal's web site is located at http://ieeexplore.ieee.org/xpl/conhome.jsp?punumber=1000290-
dc.relation.ispartofIEEE International Conference on FieId-Programmable Technology Proceedingsen_HK
dc.rightsIEEE International Conference on FieId-Programmable Technology Proceedings. Copyright © IEEE Computer Society.-
dc.rights©2009 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.-
dc.rightsCreative Commons: Attribution 3.0 Hong Kong License-
dc.subjectCommercial-off-the-shelf-
dc.subjectDesign considerations-
dc.subjectDynamic Power-
dc.subjectDynamic power consumption-
dc.subjectFPGA architectures-
dc.titleReducing dynamic power consumption in FPGAs using precomputationen_HK
dc.typeConference_Paperen_HK
dc.identifier.emailSo, HKH: skhay@hkucc.hku.hken_HK
dc.identifier.authoritySo, HKH=rp00169en_HK
dc.description.naturepublished_or_final_version-
dc.identifier.doi10.1109/FPT.2009.5377692en_HK
dc.identifier.scopuseid_2-s2.0-77949407459en_HK
dc.identifier.hkuros164926en_HK
dc.relation.referenceshttp://www.scopus.com/mlt/select.url?eid=2-s2.0-77949407459&selection=ref&src=s&origin=recordpageen_HK
dc.identifier.spage407en_HK
dc.identifier.epage410en_HK
dc.publisher.placeUnited States-
dc.identifier.scopusauthoridSo, HKH=10738896800en_HK
dc.identifier.scopusauthoridTsang, CC=35744163800en_HK
dc.customcontrol.immutablesml 140729-

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