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Conference Paper: Power optimization in a repeater-inserted interconnect via geometric programming

TitlePower optimization in a repeater-inserted interconnect via geometric programming
Authors
KeywordsGeometric programming
Interconnect
Optimization
Power
Repeater
Issue Date2006
Citation
Proceedings Of The International Symposium On Low Power Electronics And Design, 2006, v. 2006, p. 226-231 How to Cite?
AbstractWe present an innovative geometric programming (GP) approach for minimizing the power dissipation of an interconnect with repeater insertion, subject to delay, bandwidth and area constraints. Repeater sizes and segment lengths are globally optimized in various technology nodes with respect to International Technology Roadmap for Semiconductors (ITRS). Relative power dissipation due to different power components is analyzed. We show that, on average, the power dissipation per unit length can be reduced by over 30% when the timing constraint is relaxed by 5%. The optimum number of repeaters is always given as an integer in our design flow. The relationships between power dissipation and respective design constraints are easily visualized in tradeoff curves. Additional design criteria, such as reliability of the interconnect delay against process variations, are easily incorporated into the optimization. Copyright 2006 ACM.
Persistent Identifierhttp://hdl.handle.net/10722/98902
ISSN
References

 

DC FieldValueLanguage
dc.contributor.authorCeung, WTen_HK
dc.contributor.authorWong, Nen_HK
dc.date.accessioned2010-09-25T18:07:09Z-
dc.date.available2010-09-25T18:07:09Z-
dc.date.issued2006en_HK
dc.identifier.citationProceedings Of The International Symposium On Low Power Electronics And Design, 2006, v. 2006, p. 226-231en_HK
dc.identifier.issn1533-4678en_HK
dc.identifier.urihttp://hdl.handle.net/10722/98902-
dc.description.abstractWe present an innovative geometric programming (GP) approach for minimizing the power dissipation of an interconnect with repeater insertion, subject to delay, bandwidth and area constraints. Repeater sizes and segment lengths are globally optimized in various technology nodes with respect to International Technology Roadmap for Semiconductors (ITRS). Relative power dissipation due to different power components is analyzed. We show that, on average, the power dissipation per unit length can be reduced by over 30% when the timing constraint is relaxed by 5%. The optimum number of repeaters is always given as an integer in our design flow. The relationships between power dissipation and respective design constraints are easily visualized in tradeoff curves. Additional design criteria, such as reliability of the interconnect delay against process variations, are easily incorporated into the optimization. Copyright 2006 ACM.en_HK
dc.languageengen_HK
dc.relation.ispartofProceedings of the International Symposium on Low Power Electronics and Designen_HK
dc.subjectGeometric programmingen_HK
dc.subjectInterconnecten_HK
dc.subjectOptimizationen_HK
dc.subjectPoweren_HK
dc.subjectRepeateren_HK
dc.titlePower optimization in a repeater-inserted interconnect via geometric programmingen_HK
dc.typeConference_Paperen_HK
dc.identifier.emailWong, N:nwong@eee.hku.hken_HK
dc.identifier.authorityWong, N=rp00190en_HK
dc.description.naturelink_to_subscribed_fulltext-
dc.identifier.doi10.1145/1165573.1165629en_HK
dc.identifier.scopuseid_2-s2.0-34247261520en_HK
dc.identifier.hkuros133550en_HK
dc.relation.referenceshttp://www.scopus.com/mlt/select.url?eid=2-s2.0-34247261520&selection=ref&src=s&origin=recordpageen_HK
dc.identifier.volume2006en_HK
dc.identifier.spage226en_HK
dc.identifier.epage231en_HK
dc.publisher.placeUnited Statesen_HK
dc.identifier.scopusauthoridCeung, WT=16232219400en_HK
dc.identifier.scopusauthoridWong, N=35235551600en_HK

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