Effects of NO annealing on the characteristics of GaN MIS capacitor

Abstract

An ultra-thin thermally-grown GaO xN y was formed between deposited SiO 2 dielectric and GaN wafer to improve the interface quality. The interface-trap density at 0.4 eV below the conduction-band edge was reduced by one order compared with that of a sample without the stacked GaO x N y. NO annealing was conducted on both SiO 2/GaN and SiO 2/GaO x N y/GaN MIS structures, and turned out to effectively suppress the oxide charges. The sample with stacked GaO xN y annealed in NO achieved the lowest oxide-charge density (Q ox) of 1.7×10 11 cm -2 eV -1; Qox of the one without stacked GaO x N y annealed in NO was 9.5 ×10 11 cm- 2 eV- 1; those samples not annealed in NO got high Q ox of 8×10 12 cm -2 eV -1, with or without stacked GaO xN y. Moreover, NO annealing was found to effectively reduce border traps. The interface quality was improved on both the sample with the GaO xN y interlayer annealed in nitrogen and the non-stacked sample annealed in NO. The breakdown field and leakage current of the gate dielectrics were also compared in this work. © 2006 IEEE.