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Article: MISR computation algorithm for fast signature simulation

TitleMISR computation algorithm for fast signature simulation
Authors
KeywordsAlgorithms
Computer Aided Network Analysis
Computer Simulation
Error Analysis
Integrated Circuit Testing
Polynomials
State Assignment
Issue Date1996
PublisherIEEE
Citation
Proceedings of the Asian Test Symposium, 1996, p. 213-218 How to Cite?
AbstractA fast multiple input signature register (MISR) computation algorithm for signature simulation is proposed. Based on the linear compaction algorithm the modularity property of a single input signature register (SISR), and the sparsity of the error-domain input, some new accelerating schemes - partial input look-up tables and reverse zero-checking policy - are developed to boost the signature computation speed. Mathematical analysis and simulation results show that this algorithm has an order of magnitude speedup without extra memory requirement compared with the linear compaction algorithm. Though originally derived for SISR, this algorithm is applicable to MISR by a simple conversion procedure or a bit-adjusting scheme with little effort. Consequently, a very fast MISR signature simulation can be achieved.
Persistent Identifierhttp://hdl.handle.net/10722/90925
ISSN

 

DC FieldValueLanguage
dc.contributor.authorLin, Bin-Hongen_HK
dc.contributor.authorShieh, Shao-Huien_HK
dc.contributor.authorWu, Cheng-Wenen_HK
dc.date.accessioned2010-09-17T10:10:26Z-
dc.date.available2010-09-17T10:10:26Z-
dc.date.issued1996en_HK
dc.identifier.citationProceedings of the Asian Test Symposium, 1996, p. 213-218en_HK
dc.identifier.issn1081-7735en_HK
dc.identifier.urihttp://hdl.handle.net/10722/90925-
dc.description.abstractA fast multiple input signature register (MISR) computation algorithm for signature simulation is proposed. Based on the linear compaction algorithm the modularity property of a single input signature register (SISR), and the sparsity of the error-domain input, some new accelerating schemes - partial input look-up tables and reverse zero-checking policy - are developed to boost the signature computation speed. Mathematical analysis and simulation results show that this algorithm has an order of magnitude speedup without extra memory requirement compared with the linear compaction algorithm. Though originally derived for SISR, this algorithm is applicable to MISR by a simple conversion procedure or a bit-adjusting scheme with little effort. Consequently, a very fast MISR signature simulation can be achieved.en_HK
dc.languageengen_HK
dc.publisherIEEEen_HK
dc.relation.ispartofProceedings of the Asian Test Symposiumen_HK
dc.subjectAlgorithmsen_HK
dc.subjectComputer Aided Network Analysisen_HK
dc.subjectComputer Simulationen_HK
dc.subjectError Analysisen_HK
dc.subjectIntegrated Circuit Testingen_HK
dc.subjectPolynomialsen_HK
dc.subjectState Assignmenten_HK
dc.titleMISR computation algorithm for fast signature simulationen_HK
dc.typeArticleen_HK
dc.identifier.emailLin, B:blin@hku.hken_HK
dc.description.naturelink_to_subscribed_fulltext-
dc.identifier.scopuseid_2-s2.0-0030381048en_HK
dc.identifier.spage213en_HK
dc.identifier.epage218en_HK

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