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Article: A fast signature computation algorithm for LFSR and MISR
Title | A fast signature computation algorithm for LFSR and MISR |
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Authors | |
Keywords | Builtin Selftest Fault Simulation Lfsr Logic Testing Misr Signature Analysis |
Issue Date | 2000 |
Publisher | IEEE |
Citation | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2000, v. 19 n. 9, p. 10311040 How to Cite? |
Abstract | A multipleinput signature register (MISR) computation algorithm for fast signature simulation is proposed. Based on the table lookup linear compaction algorithm and the modularity property of a singleinput signature register (SISR), some new accelerating schemespartialinput lookup tables and flyingstate lookup tablesare developed to boost the signature computation speed. Mathematical analysis and simulation results show that this algorithm has an order of magnitude speedup without extra memory requirement compared with the original linear compaction algorithm. Though this algorithm is derived for SISR, a simple conversion scheme exists that can convert internalEXOR MISR to SISR. Consequently, fast MISR signature computation can be done. © 2000 IEEE. |
Persistent Identifier | http://hdl.handle.net/10722/90911 |
ISSN | 2023 Impact Factor: 2.7 2023 SCImago Journal Rankings: 0.957 |
References |
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Lin, BH | en_HK |
dc.contributor.author | Shieh, SH | en_HK |
dc.contributor.author | Wu, CW | en_HK |
dc.date.accessioned | 2010-09-17T10:10:13Z | - |
dc.date.available | 2010-09-17T10:10:13Z | - |
dc.date.issued | 2000 | en_HK |
dc.identifier.citation | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2000, v. 19 n. 9, p. 10311040 | en_HK |
dc.identifier.issn | 0278-0070 | en_HK |
dc.identifier.uri | http://hdl.handle.net/10722/90911 | - |
dc.description.abstract | A multipleinput signature register (MISR) computation algorithm for fast signature simulation is proposed. Based on the table lookup linear compaction algorithm and the modularity property of a singleinput signature register (SISR), some new accelerating schemespartialinput lookup tables and flyingstate lookup tablesare developed to boost the signature computation speed. Mathematical analysis and simulation results show that this algorithm has an order of magnitude speedup without extra memory requirement compared with the original linear compaction algorithm. Though this algorithm is derived for SISR, a simple conversion scheme exists that can convert internalEXOR MISR to SISR. Consequently, fast MISR signature computation can be done. © 2000 IEEE. | en_HK |
dc.language | eng | en_HK |
dc.publisher | IEEE | en_HK |
dc.relation.ispartof | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | en_HK |
dc.subject | Builtin Selftest | en_HK |
dc.subject | Fault Simulation | en_HK |
dc.subject | Lfsr | en_HK |
dc.subject | Logic Testing | en_HK |
dc.subject | Misr | en_HK |
dc.subject | Signature Analysis | en_HK |
dc.title | A fast signature computation algorithm for LFSR and MISR | en_HK |
dc.type | Article | en_HK |
dc.identifier.email | Lin, B:blin@hku.hk | en_HK |
dc.description.nature | link_to_subscribed_fulltext | - |
dc.identifier.scopus | eid_2-s2.0-33747451674 | en_HK |
dc.relation.references | http://www.scopus.com/mlt/select.url?eid=2-s2.0-33747451674&selection=ref&src=s&origin=recordpage | en_HK |
dc.identifier.volume | 19 | en_HK |
dc.identifier.issue | 9 | en_HK |
dc.identifier.spage | 10311040 | en_HK |
dc.identifier.issnl | 0278-0070 | - |