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Article: Analysis and design of multiple-bit high-order Σ-Δ modulator
Title | Analysis and design of multiple-bit high-order Σ-Δ modulator |
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Authors | |
Keywords | Analog To Digital Conversion Bandwidth Capacitors Computer Aided Analysis Computer Aided Design Computer Simulation Frequency Response Operational Amplifiers Signal To Noise Ratio |
Issue Date | 1997 |
Citation | Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC, 1997, p. 419-424 How to Cite? |
Abstract | The high-order Σ-Δ modulator is an appropriate approach for high-bandwidth, high-resolution A/D conversion. However, non-ideal effects such as the finite op-amp gain and the capacitor mismatch have great impacts on its performance at a low oversampling ratio. To achieve greater performance under the inevitable non-ideal effects, we explore several multiple-bit schemes, based on our CIQE high-order Σ-Δ architecture, to remove the non-ideal deterioration. Design rules of these multiple-bit schemes are developed and verified by extensive simulations. |
Persistent Identifier | http://hdl.handle.net/10722/90871 |
DC Field | Value | Language |
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dc.contributor.author | Hong, Hao-Chiao | en_HK |
dc.contributor.author | Lin, Bin-Hong | en_HK |
dc.contributor.author | Wu, Cheng-Wen | en_HK |
dc.date.accessioned | 2010-09-17T10:09:38Z | - |
dc.date.available | 2010-09-17T10:09:38Z | - |
dc.date.issued | 1997 | en_HK |
dc.identifier.citation | Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC, 1997, p. 419-424 | en_HK |
dc.identifier.uri | http://hdl.handle.net/10722/90871 | - |
dc.description.abstract | The high-order Σ-Δ modulator is an appropriate approach for high-bandwidth, high-resolution A/D conversion. However, non-ideal effects such as the finite op-amp gain and the capacitor mismatch have great impacts on its performance at a low oversampling ratio. To achieve greater performance under the inevitable non-ideal effects, we explore several multiple-bit schemes, based on our CIQE high-order Σ-Δ architecture, to remove the non-ideal deterioration. Design rules of these multiple-bit schemes are developed and verified by extensive simulations. | en_HK |
dc.language | eng | en_HK |
dc.relation.ispartof | Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC | en_HK |
dc.subject | Analog To Digital Conversion | en_HK |
dc.subject | Bandwidth | en_HK |
dc.subject | Capacitors | en_HK |
dc.subject | Computer Aided Analysis | en_HK |
dc.subject | Computer Aided Design | en_HK |
dc.subject | Computer Simulation | en_HK |
dc.subject | Frequency Response | en_HK |
dc.subject | Operational Amplifiers | en_HK |
dc.subject | Signal To Noise Ratio | en_HK |
dc.title | Analysis and design of multiple-bit high-order Σ-Δ modulator | en_HK |
dc.type | Article | en_HK |
dc.identifier.email | Lin, B:blin@hku.hk | en_HK |
dc.description.nature | link_to_subscribed_fulltext | - |
dc.identifier.scopus | eid_2-s2.0-0030702998 | en_HK |
dc.identifier.spage | 419 | en_HK |
dc.identifier.epage | 424 | en_HK |