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Article: Degradation measurements using fully processed test transistors in high density plasma reactors for failure analysis

TitleDegradation measurements using fully processed test transistors in high density plasma reactors for failure analysis
Authors
Issue Date1997
PublisherAmerican Vacuum Society. The Journal's web site is located at http://www.avs.org/literature.jvst.b.aspx
Citation
Journal Of Vacuum Science And Technology B: Microelectronics And Nanometer Structures, 1997, v. 15 n. 6, p. 1913-1918 How to Cite?
AbstractThe objective of this study was for it to serve as a guide for understanding high density plasma induced damage during wafer fabrication and etchback for device debug, electron-beam, and failure analysis. A study of electrical degradation of packaged and fully processed transistors that were functionally etched back was carried out. Two high density plasma technologies, electron cyclotron resonance (ECR) and inductively coupled plasma (ICP), from various vendors, were evaluated. Transconductance (gm), threshold voltage (Vt), subthreshold slope, and gate leakage (Ig) were measured before and after the functional etch. Degradation took place even without polysilicon being directly exposed to the plasma. It was found that there is a strong correlation between the threshold voltage shift, and gate current shift, and they exhibit a bimodal relationship. The gate edge intensive transistor was most susceptible to degradation. The design of the etchers seemed to be the key factor rather than the choice of technology (ECR or ICP) with regard to transistor degradation. Gate oxide breakdown due to the charging of metal lines, caused by nonuniform electrical charging of the surface, adequately explains the observed transistor parameter shifts. © 1997 American Vacuum Society.
Persistent Identifierhttp://hdl.handle.net/10722/83853
ISSN
2015 Impact Factor: 1.398
References

 

DC FieldValueLanguage
dc.contributor.authorMuniandy, Ren_HK
dc.contributor.authorBoylan, Ren_HK
dc.contributor.authorChin, Ren_HK
dc.contributor.authorBell, Nen_HK
dc.contributor.authorSankman, Ren_HK
dc.date.accessioned2010-09-06T08:46:00Z-
dc.date.available2010-09-06T08:46:00Z-
dc.date.issued1997en_HK
dc.identifier.citationJournal Of Vacuum Science And Technology B: Microelectronics And Nanometer Structures, 1997, v. 15 n. 6, p. 1913-1918en_HK
dc.identifier.issn1071-1023en_HK
dc.identifier.urihttp://hdl.handle.net/10722/83853-
dc.description.abstractThe objective of this study was for it to serve as a guide for understanding high density plasma induced damage during wafer fabrication and etchback for device debug, electron-beam, and failure analysis. A study of electrical degradation of packaged and fully processed transistors that were functionally etched back was carried out. Two high density plasma technologies, electron cyclotron resonance (ECR) and inductively coupled plasma (ICP), from various vendors, were evaluated. Transconductance (gm), threshold voltage (Vt), subthreshold slope, and gate leakage (Ig) were measured before and after the functional etch. Degradation took place even without polysilicon being directly exposed to the plasma. It was found that there is a strong correlation between the threshold voltage shift, and gate current shift, and they exhibit a bimodal relationship. The gate edge intensive transistor was most susceptible to degradation. The design of the etchers seemed to be the key factor rather than the choice of technology (ECR or ICP) with regard to transistor degradation. Gate oxide breakdown due to the charging of metal lines, caused by nonuniform electrical charging of the surface, adequately explains the observed transistor parameter shifts. © 1997 American Vacuum Society.en_HK
dc.publisherAmerican Vacuum Society. The Journal's web site is located at http://www.avs.org/literature.jvst.b.aspxen_HK
dc.relation.ispartofJournal of Vacuum Science and Technology B: Microelectronics and Nanometer Structuresen_HK
dc.titleDegradation measurements using fully processed test transistors in high density plasma reactors for failure analysisen_HK
dc.typeArticleen_HK
dc.identifier.emailChin, R: rchin@hku.hken_HK
dc.identifier.authorityChin, R=rp01300en_HK
dc.description.naturelink_to_subscribed_fulltext-
dc.identifier.scopuseid_2-s2.0-0041401682en_HK
dc.relation.referenceshttp://www.scopus.com/mlt/select.url?eid=2-s2.0-0041401682&selection=ref&src=s&origin=recordpageen_HK
dc.identifier.volume15en_HK
dc.identifier.issue6en_HK
dc.identifier.spage1913en_HK
dc.identifier.epage1918en_HK
dc.publisher.placeUnited Statesen_HK
dc.identifier.scopusauthoridMuniandy, R=6507790101en_HK
dc.identifier.scopusauthoridBoylan, R=7003747215en_HK
dc.identifier.scopusauthoridChin, R=7102445426en_HK
dc.identifier.scopusauthoridBell, N=7201759104en_HK
dc.identifier.scopusauthoridSankman, R=36979256700en_HK

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