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Article: Quad-level bit-stream adders and multipliers with efficient FPGA implementation

TitleQuad-level bit-stream adders and multipliers with efficient FPGA implementation
Authors
Issue Date2008
PublisherThe Institution of Engineering and Technology. The Journal's web site is located at http://www.ieedl.org/EL
Citation
Electronics Letters, 2008, v. 44 n. 12, p. 722-724 How to Cite?
AbstractNovel adder and multiplier circuits for bit-stream signal processing customised for quad-level sigma-delta modulated signals are proposed. Compared with existing sorter-based quad-level sigma-delta adders and multipliers, the proposed implementation is more resource-efficient (>76 hardware savings) and faster (>93 higher clock frequency) when realised on state-of-the-art FPGA architecture featuring six-input look-up tables. © 2008 The Institution of Engineering and Technology.
Persistent Identifierhttp://hdl.handle.net/10722/73707
ISSN
2015 Impact Factor: 0.854
2015 SCImago Journal Rankings: 0.549
ISI Accession Number ID
References

 

DC FieldValueLanguage
dc.contributor.authorNg, CWen_HK
dc.contributor.authorWong, Nen_HK
dc.contributor.authorNg, TSen_HK
dc.date.accessioned2010-09-06T06:53:59Z-
dc.date.available2010-09-06T06:53:59Z-
dc.date.issued2008en_HK
dc.identifier.citationElectronics Letters, 2008, v. 44 n. 12, p. 722-724en_HK
dc.identifier.issn0013-5194en_HK
dc.identifier.urihttp://hdl.handle.net/10722/73707-
dc.description.abstractNovel adder and multiplier circuits for bit-stream signal processing customised for quad-level sigma-delta modulated signals are proposed. Compared with existing sorter-based quad-level sigma-delta adders and multipliers, the proposed implementation is more resource-efficient (>76 hardware savings) and faster (>93 higher clock frequency) when realised on state-of-the-art FPGA architecture featuring six-input look-up tables. © 2008 The Institution of Engineering and Technology.en_HK
dc.languageengen_HK
dc.publisherThe Institution of Engineering and Technology. The Journal's web site is located at http://www.ieedl.org/ELen_HK
dc.relation.ispartofElectronics Lettersen_HK
dc.titleQuad-level bit-stream adders and multipliers with efficient FPGA implementationen_HK
dc.typeArticleen_HK
dc.identifier.emailWong, N:nwong@eee.hku.hken_HK
dc.identifier.emailNg, TS:tsng@eee.hku.hken_HK
dc.identifier.authorityWong, N=rp00190en_HK
dc.identifier.authorityNg, TS=rp00159en_HK
dc.description.naturelink_to_subscribed_fulltext-
dc.identifier.doi10.1049/el:20080547en_HK
dc.identifier.scopuseid_2-s2.0-44649162081en_HK
dc.identifier.hkuros152259en_HK
dc.relation.referenceshttp://www.scopus.com/mlt/select.url?eid=2-s2.0-44649162081&selection=ref&src=s&origin=recordpageen_HK
dc.identifier.volume44en_HK
dc.identifier.issue12en_HK
dc.identifier.spage722en_HK
dc.identifier.epage724en_HK
dc.identifier.isiWOS:000256813200012-
dc.publisher.placeUnited Kingdomen_HK
dc.identifier.scopusauthoridNg, CW=36747471300en_HK
dc.identifier.scopusauthoridWong, N=35235551600en_HK
dc.identifier.scopusauthoridNg, TS=7402229975en_HK

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