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Article: A one-pass thinning algorithm and its parallel implementation

TitleA one-pass thinning algorithm and its parallel implementation
Authors
KeywordsIMAGE PROCESSING
LOGIC DEVICES - Gates
Issue Date1987
Citation
Computer Vision, Graphics And Image Processing, 1987, v. 40 n. 1, p. 30-40 How to Cite?
AbstractThis paper describes a one-pass thinning algorithm that requires only a single cycle of parallel operations per iteration. The major difference between this algorithm and the usual multiple-pass 3 × 3 operators is that it uses two restoring templates (a 1 × 4 and a 4 × 1 operator) to deal with the breakage and disappearance of horizontal and vertical two pixel wide limbs. Connectedness of skeletons has been verified and limitations of the algorithm have been discussed. Results of a comparative study are also presented. In addition, a realization of the thinning algorithm is suggested with processing speed limited only to the propagation delays of logic gates. © 1987.
Persistent Identifierhttp://hdl.handle.net/10722/65548
ISSN

 

DC FieldValueLanguage
dc.contributor.authorChin, RTen_HK
dc.contributor.authorWan, HKen_HK
dc.contributor.authorStover, DLen_HK
dc.contributor.authorIverson, RDen_HK
dc.date.accessioned2010-08-31T07:15:17Z-
dc.date.available2010-08-31T07:15:17Z-
dc.date.issued1987en_HK
dc.identifier.citationComputer Vision, Graphics And Image Processing, 1987, v. 40 n. 1, p. 30-40en_HK
dc.identifier.issn0734-189Xen_HK
dc.identifier.urihttp://hdl.handle.net/10722/65548-
dc.description.abstractThis paper describes a one-pass thinning algorithm that requires only a single cycle of parallel operations per iteration. The major difference between this algorithm and the usual multiple-pass 3 × 3 operators is that it uses two restoring templates (a 1 × 4 and a 4 × 1 operator) to deal with the breakage and disappearance of horizontal and vertical two pixel wide limbs. Connectedness of skeletons has been verified and limitations of the algorithm have been discussed. Results of a comparative study are also presented. In addition, a realization of the thinning algorithm is suggested with processing speed limited only to the propagation delays of logic gates. © 1987.en_HK
dc.languageengen_HK
dc.relation.ispartofComputer Vision, Graphics and Image Processingen_HK
dc.subjectIMAGE PROCESSINGen_HK
dc.subjectLOGIC DEVICES - Gatesen_HK
dc.titleA one-pass thinning algorithm and its parallel implementationen_HK
dc.typeArticleen_HK
dc.identifier.emailChin, RT: rchin@hku.hken_HK
dc.identifier.authorityChin, RT=rp01300en_HK
dc.description.naturelink_to_subscribed_fulltexten_HK
dc.identifier.scopuseid_2-s2.0-0023523495en_HK
dc.identifier.volume40en_HK
dc.identifier.issue1en_HK
dc.identifier.spage30en_HK
dc.identifier.epage40en_HK
dc.identifier.scopusauthoridChin, RT=7102445426en_HK
dc.identifier.scopusauthoridWan, HK=7201661077en_HK
dc.identifier.scopusauthoridStover, DL=7103223119en_HK
dc.identifier.scopusauthoridIverson, RD=7005962963en_HK

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