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Article: A one-pass thinning algorithm and its parallel implementation
Title | A one-pass thinning algorithm and its parallel implementation |
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Authors | |
Keywords | IMAGE PROCESSING LOGIC DEVICES - Gates |
Issue Date | 1987 |
Citation | Computer Vision, Graphics And Image Processing, 1987, v. 40 n. 1, p. 30-40 How to Cite? |
Abstract | This paper describes a one-pass thinning algorithm that requires only a single cycle of parallel operations per iteration. The major difference between this algorithm and the usual multiple-pass 3 × 3 operators is that it uses two restoring templates (a 1 × 4 and a 4 × 1 operator) to deal with the breakage and disappearance of horizontal and vertical two pixel wide limbs. Connectedness of skeletons has been verified and limitations of the algorithm have been discussed. Results of a comparative study are also presented. In addition, a realization of the thinning algorithm is suggested with processing speed limited only to the propagation delays of logic gates. © 1987. |
Persistent Identifier | http://hdl.handle.net/10722/65548 |
ISSN | |
ISI Accession Number ID |
DC Field | Value | Language |
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dc.contributor.author | Chin, RT | en_HK |
dc.contributor.author | Wan, HK | en_HK |
dc.contributor.author | Stover, DL | en_HK |
dc.contributor.author | Iverson, RD | en_HK |
dc.date.accessioned | 2010-08-31T07:15:17Z | - |
dc.date.available | 2010-08-31T07:15:17Z | - |
dc.date.issued | 1987 | en_HK |
dc.identifier.citation | Computer Vision, Graphics And Image Processing, 1987, v. 40 n. 1, p. 30-40 | en_HK |
dc.identifier.issn | 0734-189X | en_HK |
dc.identifier.uri | http://hdl.handle.net/10722/65548 | - |
dc.description.abstract | This paper describes a one-pass thinning algorithm that requires only a single cycle of parallel operations per iteration. The major difference between this algorithm and the usual multiple-pass 3 × 3 operators is that it uses two restoring templates (a 1 × 4 and a 4 × 1 operator) to deal with the breakage and disappearance of horizontal and vertical two pixel wide limbs. Connectedness of skeletons has been verified and limitations of the algorithm have been discussed. Results of a comparative study are also presented. In addition, a realization of the thinning algorithm is suggested with processing speed limited only to the propagation delays of logic gates. © 1987. | en_HK |
dc.language | eng | en_HK |
dc.relation.ispartof | Computer Vision, Graphics and Image Processing | en_HK |
dc.subject | IMAGE PROCESSING | en_HK |
dc.subject | LOGIC DEVICES - Gates | en_HK |
dc.title | A one-pass thinning algorithm and its parallel implementation | en_HK |
dc.type | Article | en_HK |
dc.identifier.email | Chin, RT: rchin@hku.hk | en_HK |
dc.identifier.authority | Chin, RT=rp01300 | en_HK |
dc.description.nature | link_to_subscribed_fulltext | en_HK |
dc.identifier.scopus | eid_2-s2.0-0023523495 | en_HK |
dc.identifier.volume | 40 | en_HK |
dc.identifier.issue | 1 | en_HK |
dc.identifier.spage | 30 | en_HK |
dc.identifier.epage | 40 | en_HK |
dc.identifier.isi | WOS:A1987K067200002 | - |
dc.identifier.scopusauthorid | Chin, RT=7102445426 | en_HK |
dc.identifier.scopusauthorid | Wan, HK=7201661077 | en_HK |
dc.identifier.scopusauthorid | Stover, DL=7103223119 | en_HK |
dc.identifier.scopusauthorid | Iverson, RD=7005962963 | en_HK |
dc.identifier.issnl | 0734-189X | - |