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Conference Paper: Threshold-voltage instability of polymer thin-film transistor under gate-bias and drain-bias stresses

TitleThreshold-voltage instability of polymer thin-film transistor under gate-bias and drain-bias stresses
Authors
KeywordsThreshold-voltage shift
Stress effect
Stability
Polymer thin-film transistors
Issue Date2008
PublisherIEEE. The Journal's web site is located at http://ieeexplore.ieee.org/xpl/conhome.jsp?punumber=1000853
Citation
The 2008 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC), Hong Kong, China, 8-10 December 2008. In Conference Proceedings, 2008, p. 1-4 How to Cite?
AbstractPolymer thin-film transistors (PTFTs) based on MEH-PPV semiconductor are fabricated by spin-coating process and characterized. Gate-bias and drain-bias stress effects at room temperature are observed in the devices. The saturation current decreases and the threshold voltage shifts toward negative direction upon the gate-bias stress. However, the saturation current increases and the threshold voltage shifts toward positive direction upon the drain-bias stress. For variable bias stress conditions, carrier mobility is almost unchanged. The results suggest that the origin of threshold-voltage shift upon negative gate-bias stress is predominantly associated with holes trapped within the SiO 2 gate dielectric or at the SiO 2/Si interface due to hotcarrier emission under high gate-bias stress, while time-dependent charge trapping into the deep trap states in the channel region is responsible for the drain-bias stress effect in the PTFTs. © 2008 IEEE.
Persistent Identifierhttp://hdl.handle.net/10722/62095
ISBN
References

 

DC FieldValueLanguage
dc.contributor.authorLiu, Yen_HK
dc.contributor.authorYu, JLen_HK
dc.contributor.authorLai, PTen_HK
dc.contributor.authorWang, ZXen_HK
dc.contributor.authorHan, Jen_HK
dc.contributor.authorLiao, Ren_HK
dc.date.accessioned2010-07-13T03:53:47Z-
dc.date.available2010-07-13T03:53:47Z-
dc.date.issued2008en_HK
dc.identifier.citationThe 2008 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC), Hong Kong, China, 8-10 December 2008. In Conference Proceedings, 2008, p. 1-4en_HK
dc.identifier.isbn978-1-4244-2540-2-
dc.identifier.urihttp://hdl.handle.net/10722/62095-
dc.description.abstractPolymer thin-film transistors (PTFTs) based on MEH-PPV semiconductor are fabricated by spin-coating process and characterized. Gate-bias and drain-bias stress effects at room temperature are observed in the devices. The saturation current decreases and the threshold voltage shifts toward negative direction upon the gate-bias stress. However, the saturation current increases and the threshold voltage shifts toward positive direction upon the drain-bias stress. For variable bias stress conditions, carrier mobility is almost unchanged. The results suggest that the origin of threshold-voltage shift upon negative gate-bias stress is predominantly associated with holes trapped within the SiO 2 gate dielectric or at the SiO 2/Si interface due to hotcarrier emission under high gate-bias stress, while time-dependent charge trapping into the deep trap states in the channel region is responsible for the drain-bias stress effect in the PTFTs. © 2008 IEEE.en_HK
dc.languageengen_HK
dc.publisherIEEE. The Journal's web site is located at http://ieeexplore.ieee.org/xpl/conhome.jsp?punumber=1000853-
dc.relation.ispartofIEEE Conference on Electron Devices and Solid-State Circuits Proceedingsen_HK
dc.rightsIEEE Conference on Electron Devices and Solid-State Circuits Proceedings. Copyright © IEEE.-
dc.rights©2008 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.-
dc.rightsCreative Commons: Attribution 3.0 Hong Kong License-
dc.subjectThreshold-voltage shiften_HK
dc.subjectStress effecten_HK
dc.subjectStabilityen_HK
dc.subjectPolymer thin-film transistorsen_HK
dc.titleThreshold-voltage instability of polymer thin-film transistor under gate-bias and drain-bias stressesen_HK
dc.typeConference_Paperen_HK
dc.identifier.emailLai, PT: laip@eee.hku.hken_HK
dc.identifier.authorityLai, PT=rp00130en_HK
dc.description.naturepublished_or_final_version-
dc.identifier.doi10.1109/EDSSC.2008.4760739en_HK
dc.identifier.scopuseid_2-s2.0-63249129221en_HK
dc.identifier.hkuros164341en_HK
dc.relation.referenceshttp://www.scopus.com/mlt/select.url?eid=2-s2.0-63249129221&selection=ref&src=s&origin=recordpageen_HK
dc.identifier.spage1-
dc.identifier.epage4-
dc.publisher.placeUnited States-
dc.identifier.scopusauthoridLiao, R=36655841600en_HK
dc.identifier.scopusauthoridHan, J=25642775400en_HK
dc.identifier.scopusauthoridWang, ZX=35207091700en_HK
dc.identifier.scopusauthoridLai, PT=7202946460en_HK
dc.identifier.scopusauthoridYu, JL=35207754800en_HK
dc.identifier.scopusauthoridLiu, YR=36062331200en_HK
dc.customcontrol.immutablesml 140527-

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