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Conference Paper: Direct sigma-delta modulated signal processing in FPGA

TitleDirect sigma-delta modulated signal processing in FPGA
Authors
KeywordsComputer hardware description languages
Field programmable gate arrays (fpga)
Frequency multiplying circuits
Signal processing
Clock frequencies
Issue Date2008
PublisherIEEE.
Citation
The International Conference on Field Programmable Logic and Applications (FPL 2008), Heidelberg, Germany, 8-10 September 2008. In Proceedings of FPL, 2008, p. 475-478 How to Cite?
AbstractThe effectiveness of implementing bit-stream signal processing (BSSP) multiplier circuits in FPGAs, in terms of hardware resources and clock frequency, is presented. In particular, the result of realizing BSSP multipliers on FPGA architectures that utilize 6-input lookup tables (LUTs) is compared against architectures that utilize 4-input LUTs. It is found that architectures featuring 6-input LUTs suit well in BSSP applications where wide combinatorial paths are common. Furthermore, the performance of a BSSP multiplier is compared against conventional parallel multipliers in terms of LUT resource requirements. For a given resource requirement, it is found that an over-sampling ratio of less than 32 is required for a BSSP multiplier to outperform its parallel counterpart. ©2008 IEEE.
Persistent Identifierhttp://hdl.handle.net/10722/61965
ISBN
References

 

DC FieldValueLanguage
dc.contributor.authorNg, CWen_HK
dc.contributor.authorWong, Nen_HK
dc.contributor.authorSo, HKHen_HK
dc.contributor.authorNg, TSen_HK
dc.date.accessioned2010-07-13T03:51:08Z-
dc.date.available2010-07-13T03:51:08Z-
dc.date.issued2008en_HK
dc.identifier.citationThe International Conference on Field Programmable Logic and Applications (FPL 2008), Heidelberg, Germany, 8-10 September 2008. In Proceedings of FPL, 2008, p. 475-478en_HK
dc.identifier.isbn978-1-4244-1960-9-
dc.identifier.urihttp://hdl.handle.net/10722/61965-
dc.description.abstractThe effectiveness of implementing bit-stream signal processing (BSSP) multiplier circuits in FPGAs, in terms of hardware resources and clock frequency, is presented. In particular, the result of realizing BSSP multipliers on FPGA architectures that utilize 6-input lookup tables (LUTs) is compared against architectures that utilize 4-input LUTs. It is found that architectures featuring 6-input LUTs suit well in BSSP applications where wide combinatorial paths are common. Furthermore, the performance of a BSSP multiplier is compared against conventional parallel multipliers in terms of LUT resource requirements. For a given resource requirement, it is found that an over-sampling ratio of less than 32 is required for a BSSP multiplier to outperform its parallel counterpart. ©2008 IEEE.en_HK
dc.languageengen_HK
dc.publisherIEEE.-
dc.relation.ispartofProceedings of the International Conference on Field Programmable Logic and Applications, FPL 2008en_HK
dc.rightsCreative Commons: Attribution 3.0 Hong Kong License-
dc.rightsInternational Conference on Field Programmable Logic and Applications. Copyright © IEEE.-
dc.rights©2008 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.-
dc.subjectComputer hardware description languages-
dc.subjectField programmable gate arrays (fpga)-
dc.subjectFrequency multiplying circuits-
dc.subjectSignal processing-
dc.subjectClock frequencies-
dc.titleDirect sigma-delta modulated signal processing in FPGAen_HK
dc.typeConference_Paperen_HK
dc.identifier.openurlhttp://library.hku.hk:4550/resserv?sid=HKU:IR&issn=978-1-4244-1960-9&volume=&spage=475&epage=478&date=2008&atitle=Direct+sigma-delta+modulated+signal+processing+in+FPGA-
dc.identifier.emailWong, N:nwong@eee.hku.hken_HK
dc.identifier.emailSo, HKH:hso@eee.hku.hken_HK
dc.identifier.emailNg, TS:tsng@eee.hku.hken_HK
dc.identifier.authorityWong, N=rp00190en_HK
dc.identifier.authoritySo, HKH=rp00169en_HK
dc.identifier.authorityNg, TS=rp00159en_HK
dc.description.naturepublished_or_final_version-
dc.identifier.doi10.1109/FPL.2008.4629987en_HK
dc.identifier.scopuseid_2-s2.0-54949136167en_HK
dc.identifier.hkuros164749en_HK
dc.relation.referenceshttp://www.scopus.com/mlt/select.url?eid=2-s2.0-54949136167&selection=ref&src=s&origin=recordpageen_HK
dc.identifier.spage475en_HK
dc.identifier.epage478en_HK
dc.description.otherThe International Conference on Field Programmable Logic and Applications (FPL 2008), Heidelberg, Germany, 8-10 September 2008. In Proceedings of FPL, 2008, p. 475-478-
dc.identifier.scopusauthoridNg, CW=36747471300en_HK
dc.identifier.scopusauthoridWong, N=35235551600en_HK
dc.identifier.scopusauthoridSo, HKH=10738896800en_HK
dc.identifier.scopusauthoridNg, TS=7402229975en_HK

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