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Conference Paper: Quad-level bit-stream signal processing on FPGAs

TitleQuad-level bit-stream signal processing on FPGAs
Authors
KeywordsPhase locked loops
Phase shift
Quadrature phase shift keying
Signal processing
Application examples
Issue Date2008
PublisherIEEE.
Citation
The IEEE International Conference on ICECE Technology (FPT 2008), Taipei, Taiwan, 8-10 December 2008. In Proceedings of ICFPT, 2008, p. 309-312 How to Cite?
AbstractQuad-level bit-stream signal processing (BSSP) circuits are implemented and their performances are compared with previously published tri-level and bi-level BSSP implementations on FPGAs. BSSP refers to the process of performing computation directly on over-sampled delta-sigma modulated signals to eliminate the need of resource consuming decimators and interpolators. Quad-level BSSP offers better performance than their bi-and tri-level counterparts at the expense of higher resource utilization. Using a digital phase locked loop (DPLL) and a quadrature phase-shift keying (QPSK) demodulator as application examples, the effectiveness of quad-level BSSP on FPGAs is studied. The BSSP approach will be contrasted with conventional multi-bit implementations using built-in digital signal processing blocks in modern FPGAs. © 2008 IEEE.
Persistent Identifierhttp://hdl.handle.net/10722/61960
ISBN
References

 

DC FieldValueLanguage
dc.contributor.authorNg, CWen_HK
dc.contributor.authorWong, Nen_HK
dc.contributor.authorSo, HKHen_HK
dc.contributor.authorNg, TSen_HK
dc.date.accessioned2010-07-13T03:51:02Z-
dc.date.available2010-07-13T03:51:02Z-
dc.date.issued2008en_HK
dc.identifier.citationThe IEEE International Conference on ICECE Technology (FPT 2008), Taipei, Taiwan, 8-10 December 2008. In Proceedings of ICFPT, 2008, p. 309-312en_HK
dc.identifier.isbn978-1-4244-3783-2-
dc.identifier.urihttp://hdl.handle.net/10722/61960-
dc.description.abstractQuad-level bit-stream signal processing (BSSP) circuits are implemented and their performances are compared with previously published tri-level and bi-level BSSP implementations on FPGAs. BSSP refers to the process of performing computation directly on over-sampled delta-sigma modulated signals to eliminate the need of resource consuming decimators and interpolators. Quad-level BSSP offers better performance than their bi-and tri-level counterparts at the expense of higher resource utilization. Using a digital phase locked loop (DPLL) and a quadrature phase-shift keying (QPSK) demodulator as application examples, the effectiveness of quad-level BSSP on FPGAs is studied. The BSSP approach will be contrasted with conventional multi-bit implementations using built-in digital signal processing blocks in modern FPGAs. © 2008 IEEE.en_HK
dc.languageengen_HK
dc.publisherIEEE.-
dc.relation.ispartofProceedings of the IEEE International Conference on Field-Programmable Technology, ICFPT 2008en_HK
dc.rightsIEEE International Conference on Field Programmable Technology. Copyright © IEEE.-
dc.rightsCreative Commons: Attribution 3.0 Hong Kong License-
dc.rights©2008 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.-
dc.subjectPhase locked loops-
dc.subjectPhase shift-
dc.subjectQuadrature phase shift keying-
dc.subjectSignal processing-
dc.subjectApplication examples-
dc.titleQuad-level bit-stream signal processing on FPGAsen_HK
dc.typeConference_Paperen_HK
dc.identifier.openurlhttp://library.hku.hk:4550/resserv?sid=HKU:IR&issn=978-1-4244-3783-2&volume=&spage=309&epage=312&date=2008&atitle=Quad-level+bit-stream+signal+processing+on+FPGAs-
dc.identifier.emailWong, N:nwong@eee.hku.hken_HK
dc.identifier.emailSo, HKH:hso@eee.hku.hken_HK
dc.identifier.emailNg, TS:tsng@eee.hku.hken_HK
dc.identifier.authorityWong, N=rp00190en_HK
dc.identifier.authoritySo, HKH=rp00169en_HK
dc.identifier.authorityNg, TS=rp00159en_HK
dc.description.naturepublished_or_final_version-
dc.identifier.doi10.1109/FPT.2008.4762405en_HK
dc.identifier.scopuseid_2-s2.0-63049114757en_HK
dc.identifier.hkuros164704en_HK
dc.relation.referenceshttp://www.scopus.com/mlt/select.url?eid=2-s2.0-63049114757&selection=ref&src=s&origin=recordpageen_HK
dc.identifier.spage309en_HK
dc.identifier.epage312en_HK
dc.description.otherThe IEEE International Conference on ICECE Technology (FPT 2008), Taipei, Taiwan, 8-10 December 2008. In Proceedings of ICFPT, 2008, p. 309-312-
dc.identifier.scopusauthoridNg, CW=36747471300en_HK
dc.identifier.scopusauthoridWong, N=35235551600en_HK
dc.identifier.scopusauthoridSo, HKH=10738896800en_HK
dc.identifier.scopusauthoridNg, TS=7402229975en_HK

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