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Conference Paper: Designing of precomputational-based low-power Viterbi decoder

TitleDesigning of precomputational-based low-power Viterbi decoder
Authors
Yang, JLWong, AKK
Issue Date2004
PublisherIEEE.
Citation
The 6th IEEE Circuits and Systems Symposium on Emerging Technologies: Frontiers of Mobile and Wireless Communication Proceedings, Shanghai, China, 31 May - 2 June 2004, v. 2, p. 603-606 How to Cite?
DOI: http://dx.doi.org/10.1109/CASSET.2004.1321960
AbstractThis work addresses the low-power VLSI implementation of the Viterbi decoder (VD). A new precomputational scheme applied to the trellis butterflies calculation is presented. The proposed scheme is implemented in a 16-state, rate 1/3 VD. Gate-level power verification indicates that the proposed design reduces the power dissipated by the original trellis butterflies calculation by 42%.
Persistent Identifierhttp://hdl.handle.net/10722/46505

 

DC FieldValueLanguage
dc.contributor.authorYang, JLen_HK
dc.contributor.authorWong, AKKen_HK
dc.date.accessioned2007-10-30T06:51:29Z-
dc.date.available2007-10-30T06:51:29Z-
dc.date.issued2004en_HK
dc.identifier.citationThe 6th IEEE Circuits and Systems Symposium on Emerging Technologies: Frontiers of Mobile and Wireless Communication Proceedings, Shanghai, China, 31 May - 2 June 2004, v. 2, p. 603-606en_HK
dc.identifier.urihttp://hdl.handle.net/10722/46505-
dc.description.abstractThis work addresses the low-power VLSI implementation of the Viterbi decoder (VD). A new precomputational scheme applied to the trellis butterflies calculation is presented. The proposed scheme is implemented in a 16-state, rate 1/3 VD. Gate-level power verification indicates that the proposed design reduces the power dissipated by the original trellis butterflies calculation by 42%.en_HK
dc.format.extent238954 bytes-
dc.format.extent5278 bytes-
dc.format.extent1840 bytes-
dc.format.mimetypeapplication/pdf-
dc.format.mimetypetext/plain-
dc.format.mimetypetext/plain-
dc.languageengen_HK
dc.publisherIEEE.en_HK
dc.rights©2004 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.-
dc.titleDesigning of precomputational-based low-power Viterbi decoderen_HK
dc.typeConference_Paperen_HK
dc.description.naturepublished_or_final_versionen_HK
dc.identifier.doi10.1109/CASSET.2004.1321960-
dc.identifier.scopuseid_2-s2.0-20344386251-
dc.identifier.hkuros94105-

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