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Conference Paper: Design and multiplier-less realization of matched filters with variable fractional delay for software radio receivers
Title | Design and multiplier-less realization of matched filters with variable fractional delay for software radio receivers |
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Authors | |
Keywords | Computers Circuits |
Issue Date | 2004 |
Publisher | IEEE. |
Citation | Midwest Symposium On Circuits And Systems, 2004, v. 2, p. II357-II360 How to Cite? |
Abstract | This paper studies the design and multiplier-less realization of variable fractional delay matched filters (VFD-MFs), which provide matching filtering and variable fractional delay of the filter output. It offers greater flexibility and lower delay in symbol-timing adjustment than directly cascading a match filter with a fractional delayer. The design of VFD-MFs, which can be viewed as a variable digital filter (VDF) design problem subject to the matched filtering condition, is formulated as a second order cone programming (SOCP) problem with least square design criteria. The proposed VFD-MFs can be efficiently implemented using the Farrow structure. By employing sum-of-power-of-two (SOPOT) coefficients and the multiplier block (MB) technique, very efficient multiplier-less realization of the VFD-MF with low hardware complexity is obtained. A design example is given to demonstrate the effectiveness of the proposed approach. |
Description | The 47th Midwest Symposium on Circuits and Systems Conference, Salt Lake City, Utah, USA, 25-28 July 2004 |
Persistent Identifier | http://hdl.handle.net/10722/46435 |
ISSN | 2023 SCImago Journal Rankings: 0.268 |
References |
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Chan, SC | en_HK |
dc.contributor.author | Tsui, KM | en_HK |
dc.date.accessioned | 2007-10-30T06:49:48Z | - |
dc.date.available | 2007-10-30T06:49:48Z | - |
dc.date.issued | 2004 | en_HK |
dc.identifier.citation | Midwest Symposium On Circuits And Systems, 2004, v. 2, p. II357-II360 | en_HK |
dc.identifier.issn | 1548-3746 | en_HK |
dc.identifier.uri | http://hdl.handle.net/10722/46435 | - |
dc.description | The 47th Midwest Symposium on Circuits and Systems Conference, Salt Lake City, Utah, USA, 25-28 July 2004 | - |
dc.description.abstract | This paper studies the design and multiplier-less realization of variable fractional delay matched filters (VFD-MFs), which provide matching filtering and variable fractional delay of the filter output. It offers greater flexibility and lower delay in symbol-timing adjustment than directly cascading a match filter with a fractional delayer. The design of VFD-MFs, which can be viewed as a variable digital filter (VDF) design problem subject to the matched filtering condition, is formulated as a second order cone programming (SOCP) problem with least square design criteria. The proposed VFD-MFs can be efficiently implemented using the Farrow structure. By employing sum-of-power-of-two (SOPOT) coefficients and the multiplier block (MB) technique, very efficient multiplier-less realization of the VFD-MF with low hardware complexity is obtained. A design example is given to demonstrate the effectiveness of the proposed approach. | en_HK |
dc.format.extent | 504738 bytes | - |
dc.format.extent | 2563 bytes | - |
dc.format.extent | 27162 bytes | - |
dc.format.mimetype | application/pdf | - |
dc.format.mimetype | text/plain | - |
dc.format.mimetype | text/plain | - |
dc.language | eng | en_HK |
dc.publisher | IEEE. | en_HK |
dc.relation.ispartof | Midwest Symposium on Circuits and Systems | en_HK |
dc.rights | ©2004 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE. | - |
dc.subject | Computers | en_HK |
dc.subject | Circuits | en_HK |
dc.title | Design and multiplier-less realization of matched filters with variable fractional delay for software radio receivers | en_HK |
dc.type | Conference_Paper | en_HK |
dc.identifier.openurl | http://library.hku.hk:4550/resserv?sid=HKU:IR&issn=1548-3746&volume=2&spage=357&epage=360&date=2004&atitle=Design+and+multiplier-less+realization+of+matched+filters+with+variable+fractional+delay+for+software+radio+receivers | en_HK |
dc.identifier.email | Chan, SC:scchan@eee.hku.hk | en_HK |
dc.identifier.email | Tsui, KM:kmtsui@eee.hku.hk | en_HK |
dc.identifier.authority | Chan, SC=rp00094 | en_HK |
dc.identifier.authority | Tsui, KM=rp00181 | en_HK |
dc.description.nature | published_or_final_version | en_HK |
dc.identifier.doi | 10.1109/MWSCAS.2004.1354167 | en_HK |
dc.identifier.scopus | eid_2-s2.0-11144256285 | en_HK |
dc.identifier.hkuros | 90081 | - |
dc.relation.references | http://www.scopus.com/mlt/select.url?eid=2-s2.0-11144256285&selection=ref&src=s&origin=recordpage | en_HK |
dc.identifier.volume | 2 | en_HK |
dc.identifier.spage | II357 | en_HK |
dc.identifier.epage | II360 | en_HK |
dc.publisher.place | United States | en_HK |
dc.identifier.scopusauthorid | Chan, SC=13310287100 | en_HK |
dc.identifier.scopusauthorid | Tsui, KM=7101671591 | en_HK |
dc.identifier.issnl | 1548-3746 | - |