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Conference Paper: Effects of grid-placed contacts on circuit performance

TitleEffects of grid-placed contacts on circuit performance
Authors
KeywordsResolution enhancement techniques
Grid-placed contacts
Standard cells
Double exposure
Critical dimension
Issue Date2003
PublisherS P I E - International Society for Optical Engineering. The Journal's web site is located at http://www.spie.org/app/Publications/index.cfm?fuseaction=proceedings
Citation
Cost and Performance in Integrated Circuit Creation, Santa Clara, California, USA, 27-28 February 2003. In Proceedings of SPIE, 2003, v. 5043, p. 134-141 How to Cite?
AbstractThe impact of grid-placed contacts on application-specific integrated circuit (ASIC) performance is studied. Although snapping contacts to grid adds restrictions during layout design, smaller circuit area can be achieved by careful selection of the grid pitch, raising the lower limit of transistor width, applying double exposure, and shrinking the minimum contact pitch enabled by more effective application of resolution enhancement technologies. The technique is demonstrated on the contact level of 250-nm standard cells with the minimum contact pitch shrunk by 10%. The area change of 84 cells ranges from -20% to 25% with a median decrease of 5%. The areas of two circuits, a finite-impulse-response (FIR) filter and an add-compare-select (ACS) unit in the Viterbi decoder, decrease by 4% and 2% respectively. Delay and power consumption are also estimated to decrease with area.
Persistent Identifierhttp://hdl.handle.net/10722/46396
ISSN
2023 SCImago Journal Rankings: 0.152

 

DC FieldValueLanguage
dc.contributor.authorWang, Jen_HK
dc.contributor.authorWong, AKKen_HK
dc.date.accessioned2007-10-30T06:48:58Z-
dc.date.available2007-10-30T06:48:58Z-
dc.date.issued2003en_HK
dc.identifier.citationCost and Performance in Integrated Circuit Creation, Santa Clara, California, USA, 27-28 February 2003. In Proceedings of SPIE, 2003, v. 5043, p. 134-141-
dc.identifier.issn0277-786Xen_HK
dc.identifier.urihttp://hdl.handle.net/10722/46396-
dc.description.abstractThe impact of grid-placed contacts on application-specific integrated circuit (ASIC) performance is studied. Although snapping contacts to grid adds restrictions during layout design, smaller circuit area can be achieved by careful selection of the grid pitch, raising the lower limit of transistor width, applying double exposure, and shrinking the minimum contact pitch enabled by more effective application of resolution enhancement technologies. The technique is demonstrated on the contact level of 250-nm standard cells with the minimum contact pitch shrunk by 10%. The area change of 84 cells ranges from -20% to 25% with a median decrease of 5%. The areas of two circuits, a finite-impulse-response (FIR) filter and an add-compare-select (ACS) unit in the Viterbi decoder, decrease by 4% and 2% respectively. Delay and power consumption are also estimated to decrease with area.en_HK
dc.format.extent700985 bytes-
dc.format.extent5278 bytes-
dc.format.mimetypeapplication/pdf-
dc.format.mimetypetext/plain-
dc.languageengen_HK
dc.publisherS P I E - International Society for Optical Engineering. The Journal's web site is located at http://www.spie.org/app/Publications/index.cfm?fuseaction=proceedingsen_HK
dc.relation.ispartofProceedings of SPIE-
dc.rightsCopyright 2003 Society of Photo‑Optical Instrumentation Engineers (SPIE). One print or electronic copy may be made for personal use only. Systematic reproduction and distribution, duplication of any material in this publication for a fee or for commercial purposes, and modification of the contents of the publication are prohibited. This article is available online at https://doi.org/10.1117/12.485279-
dc.subjectResolution enhancement techniquesen_HK
dc.subjectGrid-placed contactsen_HK
dc.subjectStandard cellsen_HK
dc.subjectDouble exposureen_HK
dc.subjectCritical dimensionen_HK
dc.titleEffects of grid-placed contacts on circuit performanceen_HK
dc.typeConference_Paperen_HK
dc.identifier.openurlhttp://library.hku.hk:4550/resserv?sid=HKU:IR&issn=0277-786X&volume=5043&spage=134&epage=141&date=2003&atitle=Effects+of+grid-placed+contacts+on+circuit+performanceen_HK
dc.description.naturepublished_or_final_versionen_HK
dc.identifier.doi10.1117/12.485279en_HK
dc.identifier.scopuseid_2-s2.0-0038398093-
dc.identifier.hkuros82560-
dc.identifier.issnl0277-786X-

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