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- Publisher Website: 10.1109/HKEDM.2002.1029150
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Conference Paper: Feasibility of 50-nm device manufacture by 157-nm optical lithography: an initial assessment
Title | Feasibility of 50-nm device manufacture by 157-nm optical lithography: an initial assessment |
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Authors | |
Keywords | Electronics |
Issue Date | 2002 |
Publisher | IEEE. |
Citation | IEEE Hong Kong Electron Devices Meeting Proceedings, Hong Kong, China, 22 June 2002, p. 31-34 How to Cite? |
Abstract | The normalized process latitude (NPL) is used to assess the feasibility of 50-nm device manufacture by 157-nm optical lithography. A first NPL quantification assuming steady improvement of processing technology shows that 157-nm optical lithography is infeasible. A second NPL quantification investigates the amount of technology acceleration required to make 50-nm manufacture possible. It is concluded that photolithography is a viable lithography technique for the 50-nm technology generation only with significant improvements in focus control, photomask making, photoresist contrast, as well as aberration levels. |
Persistent Identifier | http://hdl.handle.net/10722/46314 |
DC Field | Value | Language |
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dc.contributor.author | Pong, WT | en_HK |
dc.contributor.author | Wong, AKK | en_HK |
dc.date.accessioned | 2007-10-30T06:47:09Z | - |
dc.date.available | 2007-10-30T06:47:09Z | - |
dc.date.issued | 2002 | en_HK |
dc.identifier.citation | IEEE Hong Kong Electron Devices Meeting Proceedings, Hong Kong, China, 22 June 2002, p. 31-34 | en_HK |
dc.identifier.uri | http://hdl.handle.net/10722/46314 | - |
dc.description.abstract | The normalized process latitude (NPL) is used to assess the feasibility of 50-nm device manufacture by 157-nm optical lithography. A first NPL quantification assuming steady improvement of processing technology shows that 157-nm optical lithography is infeasible. A second NPL quantification investigates the amount of technology acceleration required to make 50-nm manufacture possible. It is concluded that photolithography is a viable lithography technique for the 50-nm technology generation only with significant improvements in focus control, photomask making, photoresist contrast, as well as aberration levels. | en_HK |
dc.format.extent | 342775 bytes | - |
dc.format.extent | 5278 bytes | - |
dc.format.mimetype | application/pdf | - |
dc.format.mimetype | text/plain | - |
dc.language | eng | en_HK |
dc.publisher | IEEE. | en_HK |
dc.relation.ispartof | IEEE Hong Kong Electron Devices Meeting Proceedings | - |
dc.rights | ©2002 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE. | - |
dc.subject | Electronics | en_HK |
dc.title | Feasibility of 50-nm device manufacture by 157-nm optical lithography: an initial assessment | en_HK |
dc.type | Conference_Paper | en_HK |
dc.description.nature | published_or_final_version | en_HK |
dc.identifier.doi | 10.1109/HKEDM.2002.1029150 | en_HK |
dc.identifier.scopus | eid_2-s2.0-84892005516 | - |
dc.identifier.hkuros | 71713 | - |