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Conference Paper: FPGA implementation of digital timing recovery in software radio receiver

TitleFPGA implementation of digital timing recovery in software radio receiver
Authors
Issue Date2000
PublisherIEEE Computer Society.
Citation
The 1st Asia-Pacific Conference on Quality Software Proceedings, Tianjin, China, 4-6 December 2000, p. 703-707 How to Cite?
AbstractThis paper describes an implementation of an all-digital timing recovery scheme. Squaring nonlinearity is employed to generate the timing estimate and an IIR is used to extract the spectral component at symbol rate. Hardware design is performed using VHDL and realized in FPGA. The whole design can be fitted into an Altera EPF1OK70 FPGA chip, with 95.5% utilization of logic elements and 22% utilization of memory bits. The implementation exploits features of FPGA, which enable easy implementation of look up table and variable data precision at different nodes.
Persistent Identifierhttp://hdl.handle.net/10722/46229

 

DC FieldValueLanguage
dc.contributor.authorWu, YCen_HK
dc.contributor.authorNg, TSen_HK
dc.date.accessioned2007-10-30T06:45:15Z-
dc.date.available2007-10-30T06:45:15Z-
dc.date.issued2000en_HK
dc.identifier.citationThe 1st Asia-Pacific Conference on Quality Software Proceedings, Tianjin, China, 4-6 December 2000, p. 703-707en_HK
dc.identifier.urihttp://hdl.handle.net/10722/46229-
dc.description.abstractThis paper describes an implementation of an all-digital timing recovery scheme. Squaring nonlinearity is employed to generate the timing estimate and an IIR is used to extract the spectral component at symbol rate. Hardware design is performed using VHDL and realized in FPGA. The whole design can be fitted into an Altera EPF1OK70 FPGA chip, with 95.5% utilization of logic elements and 22% utilization of memory bits. The implementation exploits features of FPGA, which enable easy implementation of look up table and variable data precision at different nodes.en_HK
dc.format.extent433156 bytes-
dc.format.extent21012 bytes-
dc.format.extent1791 bytes-
dc.format.extent21377 bytes-
dc.format.mimetypeapplication/pdf-
dc.format.mimetypetext/plain-
dc.format.mimetypetext/plain-
dc.format.mimetypetext/plain-
dc.languageengen_HK
dc.publisherIEEE Computer Society.en_HK
dc.relation.ispartof1st Asia-Pacific Conference on Quality Software Proceedings-
dc.rights©2000 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.en_HK
dc.rightsCreative Commons: Attribution 3.0 Hong Kong License-
dc.titleFPGA implementation of digital timing recovery in software radio receiveren_HK
dc.typeConference_Paperen_HK
dc.description.naturepublished_or_final_versionen_HK
dc.identifier.doi10.1109/APCCAS.2000.913617en_HK
dc.identifier.hkuros58768-

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