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Conference Paper: Two-layer parallel switching: A practical and survivable design for performance guaranteed optical packet switches
Title | Two-layer parallel switching: A practical and survivable design for performance guaranteed optical packet switches |
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Authors | |
Keywords | Optical packet switch (OPS) Parallel switching Performance guaranteed scheduling Reconfiguration overhead |
Issue Date | 2005 |
Publisher | IEEE. The Journal's web site is located at http://ieeexplore.ieee.org/xpl/conhome.jsp?punumber=1000308 |
Citation | The 2005 IEEE Global Telecommunications Conference (Globecom), St. Louis, MO., 28 November-2 December 2005. In Globecom. IEEE Global Telecommunications Conference & Exhibition Conference Record, 2005, v. 4, p. 1905-1909 How to Cite? |
Abstract | An optical packet switch (OPS) is called performance guaranteed if it can achieve 100% throughput with bounded packet delay. Presently, high speedup requirement and large packet delay are two main disadvantages in designing performance guaranteed OPS. Survivability is another important issue that must be considered for real OPS implementations. In this paper, we propose a two-layer parallel OPS architecture together with an efficient scheduling scheme to address all the above issues. The tradeoff between speedup and packet delay under this new parallel architecture is also formulated to provide more design flexibility. Compared to the single-layer OPS, our proposed solution can simultaneously reduce both speedup and packet delay. For example, a delay of 4δN slots can be achieved with a speedup of 2 in our solution (where N is the switch size and δ is the switch reconfiguration overhead), whereas the single-layer OPS needs a speedup of 6 for a delay of 7δN slots. We show that this significant improvement benefits from a careful overall design rather than simply adding an extra switching layer. © 2005 IEEE. |
Persistent Identifier | http://hdl.handle.net/10722/45946 |
ISSN | |
References |
DC Field | Value | Language |
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dc.contributor.author | Wu, B | en_HK |
dc.contributor.author | Yeung, KL | en_HK |
dc.contributor.author | Li, VOK | en_HK |
dc.date.accessioned | 2007-10-30T06:39:12Z | - |
dc.date.available | 2007-10-30T06:39:12Z | - |
dc.date.issued | 2005 | en_HK |
dc.identifier.citation | The 2005 IEEE Global Telecommunications Conference (Globecom), St. Louis, MO., 28 November-2 December 2005. In Globecom. IEEE Global Telecommunications Conference & Exhibition Conference Record, 2005, v. 4, p. 1905-1909 | en_HK |
dc.identifier.issn | 1054-5921 | en_HK |
dc.identifier.uri | http://hdl.handle.net/10722/45946 | - |
dc.description.abstract | An optical packet switch (OPS) is called performance guaranteed if it can achieve 100% throughput with bounded packet delay. Presently, high speedup requirement and large packet delay are two main disadvantages in designing performance guaranteed OPS. Survivability is another important issue that must be considered for real OPS implementations. In this paper, we propose a two-layer parallel OPS architecture together with an efficient scheduling scheme to address all the above issues. The tradeoff between speedup and packet delay under this new parallel architecture is also formulated to provide more design flexibility. Compared to the single-layer OPS, our proposed solution can simultaneously reduce both speedup and packet delay. For example, a delay of 4δN slots can be achieved with a speedup of 2 in our solution (where N is the switch size and δ is the switch reconfiguration overhead), whereas the single-layer OPS needs a speedup of 6 for a delay of 7δN slots. We show that this significant improvement benefits from a careful overall design rather than simply adding an extra switching layer. © 2005 IEEE. | en_HK |
dc.language | eng | en_HK |
dc.publisher | IEEE. The Journal's web site is located at http://ieeexplore.ieee.org/xpl/conhome.jsp?punumber=1000308 | en_HK |
dc.relation.ispartof | Globecom. IEEE Global Telecommunications Conference & Exhibition Conference Record | en_HK |
dc.rights | ©2005 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE. | - |
dc.subject | Optical packet switch (OPS) | en_HK |
dc.subject | Parallel switching | en_HK |
dc.subject | Performance guaranteed scheduling | en_HK |
dc.subject | Reconfiguration overhead | en_HK |
dc.title | Two-layer parallel switching: A practical and survivable design for performance guaranteed optical packet switches | en_HK |
dc.type | Conference_Paper | en_HK |
dc.identifier.openurl | http://library.hku.hk:4550/resserv?sid=HKU:IR&issn=1054-5921&volume=4&spage=1905&epage=1909&date=2005&atitle=Two-layer+parallel+switching:+a+practical+and+survivable+design+for+performance+guaranteed+optical+packet+switches | en_HK |
dc.identifier.email | Yeung, KL: kyeung@eee.hku.hk | en_HK |
dc.identifier.email | Li, VOK: vli@eee.hku.hk | en_HK |
dc.identifier.authority | Yeung, KL=rp00204 | en_HK |
dc.identifier.authority | Li, VOK=rp00150 | en_HK |
dc.description.nature | published_or_final_version | en_HK |
dc.identifier.doi | 10.1109/GLOCOM.2005.1577998 | en_HK |
dc.identifier.scopus | eid_2-s2.0-33846629483 | en_HK |
dc.identifier.hkuros | 105095 | - |
dc.identifier.hkuros | 123429 | - |
dc.relation.references | http://www.scopus.com/mlt/select.url?eid=2-s2.0-33846629483&selection=ref&src=s&origin=recordpage | en_HK |
dc.identifier.volume | 4 | en_HK |
dc.identifier.spage | 1905 | en_HK |
dc.identifier.epage | 1909 | en_HK |
dc.identifier.scopusauthorid | Wu, B=24605804500 | en_HK |
dc.identifier.scopusauthorid | Yeung, KL=7202424908 | en_HK |
dc.identifier.scopusauthorid | Li, VOK=7202621685 | en_HK |
dc.customcontrol.immutable | sml 151016 - merged | - |
dc.identifier.issnl | 1054-5921 | - |