Performance optimization for gridded-layout standard cells

Abstract

The grid placement of contacts and gates enables more effective use of resolution enhancement techniques, which in turn allow a reduction of critical dimensions. Although the regular placement adds restrictions during cell layout, the overall circuit area can be made smaller and the extra manufacturing cost can be kept to the lowest by a careful selection of the grid pitch, using template-trim lithography method, allowing random contact placement in the vertical direction, and using rectangular rather than square contacts. The purpose of this work is to optimize the gridded-layout-based process. The trade-off between the layout area and manufacturing cost, and the determination of the minimum grid pitch are discussed in this paper. We demonstrate that it is a 1-D scaling instead of the conventional 2-D scaling for standard cells and the narrow MOSFETs inside after the application of the gridded layout on the contact and gate levels. The corresponding effects on circuit performances, including the leakage current, are also explored.