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Conference Paper: Performance optimization for gridded-layout standard cells

TitlePerformance optimization for gridded-layout standard cells
Authors
KeywordsCircuit performance
Design for manufacturability (DFM)
Design rules
Gridded layout
Leakage current
Low-k 1 lithography
MOSFETs scaling
Multiple exposures
Resolution Enhancement Techniques (RETs)
Standard cells
Template lithography
Issue Date2004
PublisherS P I E - International Society for Optical Engineering. The Journal's web site is located at http://spie.org/x1848.xml
Citation
Proceedings Of Spie - The International Society For Optical Engineering, 2004, v. 5567 PART 1, p. 107-118 How to Cite?
AbstractThe grid placement of contacts and gates enables more effective use of resolution enhancement techniques, which in turn allow a reduction of critical dimensions. Although the regular placement adds restrictions during cell layout, the overall circuit area can be made smaller and the extra manufacturing cost can be kept to the lowest by a careful selection of the grid pitch, using template-trim lithography method, allowing random contact placement in the vertical direction, and using rectangular rather than square contacts. The purpose of this work is to optimize the gridded-layout-based process. The trade-off between the layout area and manufacturing cost, and the determination of the minimum grid pitch are discussed in this paper. We demonstrate that it is a 1-D scaling instead of the conventional 2-D scaling for standard cells and the narrow MOSFETs inside after the application of the gridded layout on the contact and gate levels. The corresponding effects on circuit performances, including the leakage current, are also explored.
Persistent Identifierhttp://hdl.handle.net/10722/45759
ISSN
References

 

DC FieldValueLanguage
dc.contributor.authorWang, Jen_HK
dc.contributor.authorWong, AKen_HK
dc.contributor.authorLam, EYen_HK
dc.date.accessioned2007-10-30T06:34:49Z-
dc.date.available2007-10-30T06:34:49Z-
dc.date.issued2004en_HK
dc.identifier.citationProceedings Of Spie - The International Society For Optical Engineering, 2004, v. 5567 PART 1, p. 107-118en_HK
dc.identifier.issn0277-786Xen_HK
dc.identifier.urihttp://hdl.handle.net/10722/45759-
dc.description.abstractThe grid placement of contacts and gates enables more effective use of resolution enhancement techniques, which in turn allow a reduction of critical dimensions. Although the regular placement adds restrictions during cell layout, the overall circuit area can be made smaller and the extra manufacturing cost can be kept to the lowest by a careful selection of the grid pitch, using template-trim lithography method, allowing random contact placement in the vertical direction, and using rectangular rather than square contacts. The purpose of this work is to optimize the gridded-layout-based process. The trade-off between the layout area and manufacturing cost, and the determination of the minimum grid pitch are discussed in this paper. We demonstrate that it is a 1-D scaling instead of the conventional 2-D scaling for standard cells and the narrow MOSFETs inside after the application of the gridded layout on the contact and gate levels. The corresponding effects on circuit performances, including the leakage current, are also explored.en_HK
dc.format.extent722295 bytes-
dc.format.extent4084 bytes-
dc.format.mimetypeapplication/pdf-
dc.format.mimetypetext/plain-
dc.languageengen_HK
dc.publisherS P I E - International Society for Optical Engineering. The Journal's web site is located at http://spie.org/x1848.xmlen_HK
dc.relation.ispartofProceedings of SPIE - The International Society for Optical Engineeringen_HK
dc.rightsCreative Commons: Attribution 3.0 Hong Kong License-
dc.rightsS P I E - the International Society for Optical Proceedings. Copyright © S P I E - International Society for Optical Engineering.en_HK
dc.rightsCopyright 2004 Society of Photo-Optical Instrumentation Engineers. This paper was published in The 24th Annual BACUS Symposium on Photomask Technology, Monterey, California, USA, 14-17 September 2004, v. 5567, p. 107-118 and is made available as an electronic reprint with permission of SPIE. One print or electronic copy may be made for personal use only. Systematic or multiple reproduction, distribution to multiple locations via electronic or other means, duplication of any material in this paper for a fee or for commercial purposes, or modification of the content of the paper are prohibited.en_HK
dc.subjectCircuit performanceen_HK
dc.subjectDesign for manufacturability (DFM)en_HK
dc.subjectDesign rulesen_HK
dc.subjectGridded layouten_HK
dc.subjectLeakage currenten_HK
dc.subjectLow-k 1 lithographyen_HK
dc.subjectMOSFETs scalingen_HK
dc.subjectMultiple exposuresen_HK
dc.subjectResolution Enhancement Techniques (RETs)en_HK
dc.subjectStandard cellsen_HK
dc.subjectTemplate lithographyen_HK
dc.titlePerformance optimization for gridded-layout standard cellsen_HK
dc.typeConference_Paperen_HK
dc.identifier.openurlhttp://library.hku.hk:4550/resserv?sid=HKU:IR&issn=0277-786X&volume=5567&spage=107&epage=118&date=2004&atitle=Performance+optimization+for+gridded-layout+standard+cellsen_HK
dc.identifier.emailLam, EY:elam@eee.hku.hken_HK
dc.identifier.authorityLam, EY=rp00131en_HK
dc.description.naturepublished_or_final_versionen_HK
dc.identifier.doi10.1117/12.569398en_HK
dc.identifier.scopuseid_2-s2.0-19844378577en_HK
dc.identifier.hkuros101038-
dc.relation.referenceshttp://www.scopus.com/mlt/select.url?eid=2-s2.0-19844378577&selection=ref&src=s&origin=recordpageen_HK
dc.identifier.volume5567en_HK
dc.identifier.issuePART 1en_HK
dc.identifier.spage107en_HK
dc.identifier.epage118en_HK
dc.publisher.placeUnited Statesen_HK
dc.identifier.scopusauthoridWang, J=8716933500en_HK
dc.identifier.scopusauthoridWong, AK=7403147663en_HK
dc.identifier.scopusauthoridLam, EY=7102890004en_HK

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