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Article: Si ion-induced instability in flatband Voltage of Si/sup +/-implanted gate oxides
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TitleSi ion-induced instability in flatband Voltage of Si/sup +/-implanted gate oxides
 
AuthorsNg, CY2
Chen, TP2
Ding, L2
Chen, Q2
Liu, Y2
Zhao, P2
Tseng, AA3
Fung, SHY1
 
KeywordsAnnealing
flatband voltage
low energy ion beam
silicon nanocrystal (nc-Si)
 
Issue Date2006
 
PublisherIEEE.
 
CitationIEEE Transactions on Electron Devices, 2006, v. 53 n. 5, p. 1280-1282 [How to Cite?]
DOI: http://dx.doi.org/10.1109/TED.2006.871841
 
AbstractEffect of the trapped Si ions in a 30-nm gate oxide implanted with Si/sup +/ at a very low energy (1.3 keV) on the flatband voltage after various thermal annealing has been examined. For the annealing at 700/spl deg/C for 20 min, although only 0.1% of the implanted Si ions remained, it can cause a flatband voltage shift of -21.3 V, and the flatband voltage shift reduces with time under a negative gate voltage showing neutralization of the trapped ions by the injected electrons from the gate. However, the annealing at 900/spl deg/C for 20 min has reduced the number of the remaining ions to the lowest limit corresponding to a flatband voltage shift of -0.1 V, and the application of the negative voltage does not change the flatband voltage. A higher annealing temperature or a longer annealing time does not show further improvement, suggesting that the annealing at 900/spl deg/C for 20 min is sufficient for eliminating the effect of the trapped ions.
 
ISSN0018-9383
2013 Impact Factor: 2.358
2013 SCImago Journal Rankings: 1.451
 
DOIhttp://dx.doi.org/10.1109/TED.2006.871841
 
ISI Accession Number IDWOS:000237369800043
 
ReferencesReferences in Scopus
 
DC FieldValue
dc.contributor.authorNg, CY
 
dc.contributor.authorChen, TP
 
dc.contributor.authorDing, L
 
dc.contributor.authorChen, Q
 
dc.contributor.authorLiu, Y
 
dc.contributor.authorZhao, P
 
dc.contributor.authorTseng, AA
 
dc.contributor.authorFung, SHY
 
dc.date.accessioned2007-10-30T06:21:39Z
 
dc.date.available2007-10-30T06:21:39Z
 
dc.date.issued2006
 
dc.description.abstractEffect of the trapped Si ions in a 30-nm gate oxide implanted with Si/sup +/ at a very low energy (1.3 keV) on the flatband voltage after various thermal annealing has been examined. For the annealing at 700/spl deg/C for 20 min, although only 0.1% of the implanted Si ions remained, it can cause a flatband voltage shift of -21.3 V, and the flatband voltage shift reduces with time under a negative gate voltage showing neutralization of the trapped ions by the injected electrons from the gate. However, the annealing at 900/spl deg/C for 20 min has reduced the number of the remaining ions to the lowest limit corresponding to a flatband voltage shift of -0.1 V, and the application of the negative voltage does not change the flatband voltage. A higher annealing temperature or a longer annealing time does not show further improvement, suggesting that the annealing at 900/spl deg/C for 20 min is sufficient for eliminating the effect of the trapped ions.
 
dc.description.naturepublished_or_final_version
 
dc.format.extent121365 bytes
 
dc.format.extent13983 bytes
 
dc.format.mimetypeapplication/pdf
 
dc.format.mimetypeapplication/pdf
 
dc.identifier.citationIEEE Transactions on Electron Devices, 2006, v. 53 n. 5, p. 1280-1282 [How to Cite?]
DOI: http://dx.doi.org/10.1109/TED.2006.871841
 
dc.identifier.doihttp://dx.doi.org/10.1109/TED.2006.871841
 
dc.identifier.hkuros115545
 
dc.identifier.isiWOS:000237369800043
 
dc.identifier.issn0018-9383
2013 Impact Factor: 2.358
2013 SCImago Journal Rankings: 1.451
 
dc.identifier.openurl
 
dc.identifier.scopuseid_2-s2.0-33646021031
 
dc.identifier.urihttp://hdl.handle.net/10722/45281
 
dc.languageeng
 
dc.publisherIEEE.
 
dc.relation.referencesReferences in Scopus
 
dc.rights©2006 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.
 
dc.rightsCreative Commons: Attribution 3.0 Hong Kong License
 
dc.subjectAnnealing
 
dc.subjectflatband voltage
 
dc.subjectlow energy ion beam
 
dc.subjectsilicon nanocrystal (nc-Si)
 
dc.titleSi ion-induced instability in flatband Voltage of Si/sup +/-implanted gate oxides
 
dc.typeArticle
 
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<contributor.author>Chen, Q</contributor.author>
<contributor.author>Liu, Y</contributor.author>
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<contributor.author>Fung, SHY</contributor.author>
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<description.abstract>Effect of the trapped Si ions in a 30-nm gate oxide implanted with Si/sup +/ at a very low energy (1.3 keV) on the flatband voltage after various thermal annealing has been examined. For the annealing at 700/spl deg/C for 20 min, although only 0.1% of the implanted Si ions remained, it can cause a flatband voltage shift of -21.3 V, and the flatband voltage shift reduces with time under a negative gate voltage showing neutralization of the trapped ions by the injected electrons from the gate. However, the annealing at 900/spl deg/C for 20 min has reduced the number of the remaining ions to the lowest limit corresponding to a flatband voltage shift of -0.1 V, and the application of the negative voltage does not change the flatband voltage. A higher annealing temperature or a longer annealing time does not show further improvement, suggesting that the annealing at 900/spl deg/C for 20 min is sufficient for eliminating the effect of the trapped ions.</description.abstract>
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Author Affiliations
  1. The University of Hong Kong
  2. Nanyang Technological University
  3. Arizona State University