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Article: Design and complexity optimization of a new digital IF for software radio receivers with prescribed output accuracy

TitleDesign and complexity optimization of a new digital IF for software radio receivers with prescribed output accuracy
Authors
KeywordsDesign and multiplier-less realization
Prescribed output accuracy
Sampling rate conversion
Software radio receiver (SRR)
Variable digital filters (VDFs)
Wordlength determination
Issue Date2007
PublisherIEEE.
Citation
Ieee Transactions On Circuits And Systems I: Regular Papers, 2007, v. 54 n. 2, p. 351-366 How to Cite?
AbstractThis paper studies the design, signal round-off noise, and complexity optimization of a new digital intermediate frequency (IF) architecture for a software radio receiver (SRR). The IF under study consists of digital filters with fixed coefficients, except for a limited number of multipliers required in the Farrow-based sampling rate converter (SRC). The fixed-coefficient filters can be implemented efficiently using sum-of-power-of-two (SOPOT) coefficients and the multiplier- block technique, which gives minimum adder realization. Apart from the multipliers required in the SRC, the digital IF can be implemented without any multiplications. While most multiplier- less filter design and realization methods address only the coefficient round-off problem by minimizing the number of SOPOT terms used, the proposed design methodology aims to minimize more realistic hardware complexity measure, such as adder cells and registers, of the digital IF subject to a given spectral and accuracy specifications. The motivation is that the complexity is closely related to the target output accuracy, which is specified statistically by its total output noise power generated by rounding the intermediate data. Two novel algorithms for optimizing the internal wordlengths of linear time-invariant systems are proposed. The first one relaxes the solution to real valued and formulates the design problem as a constrained optimization. A closed-form solution can be determined by the Lagrange multiplier method. The second one is based on a discrete optimization method called the Marginal Analysis method, and it yields the desired wordlengths in integer values. Both approaches are found to be effective and suitable to large scale systems. A design example and the field programmable gate array (FPGA) realization of a multi-standard receiver are given to demonstrate the proposed method. © 2007 IEEE.
Persistent Identifierhttp://hdl.handle.net/10722/44762
ISSN
2006 Impact Factor: 1.139
2006 SCImago Journal Rankings: 1.111
ISI Accession Number ID
References

 

DC FieldValueLanguage
dc.contributor.authorChan, SCen_HK
dc.contributor.authorTsui, KMen_HK
dc.contributor.authorYeung, KSen_HK
dc.contributor.authorYuk, TIen_HK
dc.date.accessioned2007-10-30T06:09:41Z-
dc.date.available2007-10-30T06:09:41Z-
dc.date.issued2007en_HK
dc.identifier.citationIeee Transactions On Circuits And Systems I: Regular Papers, 2007, v. 54 n. 2, p. 351-366en_HK
dc.identifier.issn1057-7122en_HK
dc.identifier.urihttp://hdl.handle.net/10722/44762-
dc.description.abstractThis paper studies the design, signal round-off noise, and complexity optimization of a new digital intermediate frequency (IF) architecture for a software radio receiver (SRR). The IF under study consists of digital filters with fixed coefficients, except for a limited number of multipliers required in the Farrow-based sampling rate converter (SRC). The fixed-coefficient filters can be implemented efficiently using sum-of-power-of-two (SOPOT) coefficients and the multiplier- block technique, which gives minimum adder realization. Apart from the multipliers required in the SRC, the digital IF can be implemented without any multiplications. While most multiplier- less filter design and realization methods address only the coefficient round-off problem by minimizing the number of SOPOT terms used, the proposed design methodology aims to minimize more realistic hardware complexity measure, such as adder cells and registers, of the digital IF subject to a given spectral and accuracy specifications. The motivation is that the complexity is closely related to the target output accuracy, which is specified statistically by its total output noise power generated by rounding the intermediate data. Two novel algorithms for optimizing the internal wordlengths of linear time-invariant systems are proposed. The first one relaxes the solution to real valued and formulates the design problem as a constrained optimization. A closed-form solution can be determined by the Lagrange multiplier method. The second one is based on a discrete optimization method called the Marginal Analysis method, and it yields the desired wordlengths in integer values. Both approaches are found to be effective and suitable to large scale systems. A design example and the field programmable gate array (FPGA) realization of a multi-standard receiver are given to demonstrate the proposed method. © 2007 IEEE.-
dc.format.extent1641436 bytes-
dc.format.extent2384 bytes-
dc.format.extent2564 bytes-
dc.format.extent27162 bytes-
dc.format.extent5199 bytes-
dc.format.mimetypeapplication/pdf-
dc.format.mimetypetext/plain-
dc.format.mimetypetext/plain-
dc.format.mimetypetext/plain-
dc.format.mimetypetext/plain-
dc.languageengen_HK
dc.publisherIEEE.en_HK
dc.relation.ispartofIEEE Transactions on Circuits and Systems I: Regular Papersen_HK
dc.rights©2007 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.en_HK
dc.rightsCreative Commons: Attribution 3.0 Hong Kong License-
dc.subjectDesign and multiplier-less realizationen_HK
dc.subjectPrescribed output accuracyen_HK
dc.subjectSampling rate conversionen_HK
dc.subjectSoftware radio receiver (SRR)en_HK
dc.subjectVariable digital filters (VDFs)en_HK
dc.subjectWordlength determinationen_HK
dc.titleDesign and complexity optimization of a new digital IF for software radio receivers with prescribed output accuracyen_HK
dc.typeArticleen_HK
dc.identifier.openurlhttp://library.hku.hk:4550/resserv?sid=HKU:IR&issn=1549-8328&volume=54&issue=2&spage=351&epage=366&date=2007&atitle=Design+and+Complexity+Optimization+of+a+New+Digital+IF+for+Software+Radio+Receivers+With+Prescribed+Output+Accuracyen_HK
dc.identifier.emailChan, SC:scchan@eee.hku.hken_HK
dc.identifier.emailTsui, KM:kmtsui@eee.hku.hken_HK
dc.identifier.emailYuk, TI:tiyuk@eee.hku.hken_HK
dc.identifier.authorityChan, SC=rp00094en_HK
dc.identifier.authorityTsui, KM=rp00181en_HK
dc.identifier.authorityYuk, TI=rp00210en_HK
dc.description.naturepublished_or_final_versionen_HK
dc.identifier.doi10.1109/TCSI.2006.886003en_HK
dc.identifier.scopuseid_2-s2.0-33947424823en_HK
dc.identifier.hkuros140415-
dc.relation.referenceshttp://www.scopus.com/mlt/select.url?eid=2-s2.0-33947424823&selection=ref&src=s&origin=recordpageen_HK
dc.identifier.volume54en_HK
dc.identifier.issue2en_HK
dc.identifier.spage351en_HK
dc.identifier.epage366en_HK
dc.identifier.isiWOS:000244311300011-
dc.publisher.placeUnited Statesen_HK
dc.identifier.scopusauthoridChan, SC=13310287100en_HK
dc.identifier.scopusauthoridTsui, KM=7101671591en_HK
dc.identifier.scopusauthoridYeung, KS=7202425050en_HK
dc.identifier.scopusauthoridYuk, TI=6603685705en_HK

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