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Article: Standard cell design with resolution-enhancement-technique-driven regularly placed contacts and gates

TitleStandard cell design with resolution-enhancement-technique-driven regularly placed contacts and gates
Authors
KeywordsCircuit performance
Design and process integration
Low-k 1, lithography
Multiple exposures
Regularly placed layout
Resolution enhancement technologies
Standard cells
Template lithography
Issue Date2005
PublisherS P I E - International Society for Optical Engineering.
Citation
Journal Of Microlithography, Microfabrication And Microsystems, 2005, v. 4 n. 1, p. 1-10 How to Cite?
AbstractThe practicability and methodology of applying resolution-enhancement- technique-driven regularly placed contacts and gates on standard cell layout design are studied. The regular placement enables more effective use of resolution enhancement techniques (RETs), which in turn enables a reduction of critical dimensions. Although regular placement of contacts and gates adds restrictions during cell layout, the over-all circuit area can be made smaller and the number of extra masks and exposures can be kept to the lowest by careful selection of the grid pitch, using template-trim chromeless phase-shifting lithography approaches, enabling unrestricted contact placement in one direction, and using rectangular rather than square contacts. Four different fabrication-friendly layouts are compared. The average area change of 64 standard cells in a 130-nm library range from -4.2 to -15.8% with the four fabricationfriendly layout approaches. The area change of five test circuits using the four approaches range from -16.2 to +2.6%. Dynamic power consumption and intrinsic delay also improve with the decrease in circuits area, which is verified with the examination results. © 2005 Society of Pnoto-Optical Instrumentation Engineers.
Persistent Identifierhttp://hdl.handle.net/10722/44719
ISSN
2009 Impact Factor: 0.541
ISI Accession Number ID
References

 

DC FieldValueLanguage
dc.contributor.authorWang, Jen_HK
dc.contributor.authorWong, AKen_HK
dc.contributor.authorLam, EYen_HK
dc.date.accessioned2007-10-30T06:08:41Z-
dc.date.available2007-10-30T06:08:41Z-
dc.date.issued2005en_HK
dc.identifier.citationJournal Of Microlithography, Microfabrication And Microsystems, 2005, v. 4 n. 1, p. 1-10en_HK
dc.identifier.issn1537-1646en_HK
dc.identifier.urihttp://hdl.handle.net/10722/44719-
dc.description.abstractThe practicability and methodology of applying resolution-enhancement- technique-driven regularly placed contacts and gates on standard cell layout design are studied. The regular placement enables more effective use of resolution enhancement techniques (RETs), which in turn enables a reduction of critical dimensions. Although regular placement of contacts and gates adds restrictions during cell layout, the over-all circuit area can be made smaller and the number of extra masks and exposures can be kept to the lowest by careful selection of the grid pitch, using template-trim chromeless phase-shifting lithography approaches, enabling unrestricted contact placement in one direction, and using rectangular rather than square contacts. Four different fabrication-friendly layouts are compared. The average area change of 64 standard cells in a 130-nm library range from -4.2 to -15.8% with the four fabricationfriendly layout approaches. The area change of five test circuits using the four approaches range from -16.2 to +2.6%. Dynamic power consumption and intrinsic delay also improve with the decrease in circuits area, which is verified with the examination results. © 2005 Society of Pnoto-Optical Instrumentation Engineers.en_HK
dc.format.extent846412 bytes-
dc.format.extent4084 bytes-
dc.format.mimetypeapplication/pdf-
dc.format.mimetypetext/plain-
dc.languageengen_HK
dc.publisherS P I E - International Society for Optical Engineering.en_HK
dc.relation.ispartofJournal of Microlithography, Microfabrication and Microsystemsen_HK
dc.rightsCreative Commons: Attribution 3.0 Hong Kong License-
dc.rightsJournal of Microlithography, Microfabrication, and Microsystems. Copyright © S P I E - International Society for Optical Engineering.en_HK
dc.rightsCopyright 2005 Society of Photo-Optical Instrumentation Engineers. This paper was published in Journal of Microlithography, Microfabrication, and Microsystems, 2005, v. 4 n. 1, p. 013001 and is made available as an electronic reprint with permission of SPIE. One print or electronic copy may be made for personal use only. Systematic or multiple reproduction, distribution to multiple locations via electronic or other means, duplication of any material in this paper for a fee or for commercial purposes, or modification of the content of the paper are prohibited.en_HK
dc.subjectCircuit performanceen_HK
dc.subjectDesign and process integrationen_HK
dc.subjectLow-k 1, lithographyen_HK
dc.subjectMultiple exposuresen_HK
dc.subjectRegularly placed layouten_HK
dc.subjectResolution enhancement technologiesen_HK
dc.subjectStandard cellsen_HK
dc.subjectTemplate lithographyen_HK
dc.titleStandard cell design with resolution-enhancement-technique-driven regularly placed contacts and gatesen_HK
dc.typeArticleen_HK
dc.identifier.openurlhttp://library.hku.hk:4550/resserv?sid=HKU:IR&issn=1537-1646&volume=4&issue=1&spage=013001&epage=&date=2005&atitle=Standard+cell+design+with+resolution-enhancement-technique-driven+regularly+placed+contacts+and+gatesen_HK
dc.identifier.emailLam, EY:elam@eee.hku.hken_HK
dc.identifier.authorityLam, EY=rp00131en_HK
dc.description.naturepublished_or_final_versionen_HK
dc.identifier.doi10.1117/1.1857529en_HK
dc.identifier.scopuseid_2-s2.0-24144489825en_HK
dc.identifier.hkuros101036-
dc.relation.referenceshttp://www.scopus.com/mlt/select.url?eid=2-s2.0-24144489825&selection=ref&src=s&origin=recordpageen_HK
dc.identifier.volume4en_HK
dc.identifier.issue1en_HK
dc.identifier.spage1en_HK
dc.identifier.epage10en_HK
dc.identifier.isiWOS:000232841700007-
dc.publisher.placeUnited Statesen_HK
dc.identifier.scopusauthoridWang, J=8716933500en_HK
dc.identifier.scopusauthoridWong, AK=7403147663en_HK
dc.identifier.scopusauthoridLam, EY=7102890004en_HK

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