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Article: Parallelization methodology for video coding - an implementation on the TMS320C80

TitleParallelization methodology for video coding - an implementation on the TMS320C80
Authors
Issue Date2000
PublisherIEEE.
Citation
Ieee Transactions On Circuits And Systems For Video Technology, 2000, v. 10 n. 8, p. 1413-1425 How to Cite?
AbstractThis paper presents a parallelization methodology for video coding based on the philosophy of hiding as much communications by computation as possible. It models the task/data size, processor cache capacity, and communication contention, through a systematic decomposition and scheduling approach. With the aid of Petri-nets and task graphs for representation and analysis, it employs a triple buffering scheme to enable the functions of frame capture, management, and coding to be performed in parallel. The theoretical speedup analysis indicates that this method offers excellent communication hiding, resulting in system efficiency well above 90%. To prove its practicality, a H.261 video encoder has been implemented on a TMS320C80 system using the method. Its performance was measured, from which the speedup and efficiency figures were calculated. The only difference detected between the theoretical and measured data is the program control overhead that has not been accounted for in the theoretical model. Even with this, the measured speedup of the H.261 is 3.67 and 3.76 on four parallel processors (PPs) for QCIF and 352 × 240 video, respectively, which correspond to frame rate of 30.7 and 9.25 frames per second, and system efficiency of 91.8% and 94%, respectively. This method is particularly efficient for platforms with small number of parallel processors.
Persistent Identifierhttp://hdl.handle.net/10722/42876
ISSN
2015 Impact Factor: 2.254
2015 SCImago Journal Rankings: 1.606
References

 

DC FieldValueLanguage
dc.contributor.authorLeung, KKen_HK
dc.contributor.authorYung, NHCen_HK
dc.contributor.authorCheung, PYSen_HK
dc.date.accessioned2007-03-23T04:33:52Z-
dc.date.available2007-03-23T04:33:52Z-
dc.date.issued2000en_HK
dc.identifier.citationIeee Transactions On Circuits And Systems For Video Technology, 2000, v. 10 n. 8, p. 1413-1425en_HK
dc.identifier.issn1051-8215en_HK
dc.identifier.urihttp://hdl.handle.net/10722/42876-
dc.description.abstractThis paper presents a parallelization methodology for video coding based on the philosophy of hiding as much communications by computation as possible. It models the task/data size, processor cache capacity, and communication contention, through a systematic decomposition and scheduling approach. With the aid of Petri-nets and task graphs for representation and analysis, it employs a triple buffering scheme to enable the functions of frame capture, management, and coding to be performed in parallel. The theoretical speedup analysis indicates that this method offers excellent communication hiding, resulting in system efficiency well above 90%. To prove its practicality, a H.261 video encoder has been implemented on a TMS320C80 system using the method. Its performance was measured, from which the speedup and efficiency figures were calculated. The only difference detected between the theoretical and measured data is the program control overhead that has not been accounted for in the theoretical model. Even with this, the measured speedup of the H.261 is 3.67 and 3.76 on four parallel processors (PPs) for QCIF and 352 × 240 video, respectively, which correspond to frame rate of 30.7 and 9.25 frames per second, and system efficiency of 91.8% and 94%, respectively. This method is particularly efficient for platforms with small number of parallel processors.en_HK
dc.format.extent258898 bytes-
dc.format.extent26112 bytes-
dc.format.extent5183 bytes-
dc.format.mimetypeapplication/pdf-
dc.format.mimetypeapplication/msword-
dc.format.mimetypetext/plain-
dc.languageengen_HK
dc.publisherIEEE.en_HK
dc.relation.ispartofIEEE Transactions on Circuits and Systems for Video Technologyen_HK
dc.rightsCreative Commons: Attribution 3.0 Hong Kong License-
dc.rights©2000 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.en_HK
dc.titleParallelization methodology for video coding - an implementation on the TMS320C80en_HK
dc.typeArticleen_HK
dc.identifier.openurlhttp://library.hku.hk:4550/resserv?sid=HKU:IR&issn=1051-8215&volume=10&issue=8&spage=1413&epage=1425&date=2000&atitle=Parallelization+methodology+for+video+coding-an+implementation+on+the+TMS320C80en_HK
dc.identifier.emailYung, NHC:nyung@eee.hku.hken_HK
dc.identifier.emailCheung, PYS:paul.cheung@hku.hken_HK
dc.identifier.authorityYung, NHC=rp00226en_HK
dc.identifier.authorityCheung, PYS=rp00077en_HK
dc.description.naturepublished_or_final_versionen_HK
dc.identifier.doi10.1109/76.889035en_HK
dc.identifier.scopuseid_2-s2.0-0034507010en_HK
dc.identifier.hkuros60586-
dc.relation.referenceshttp://www.scopus.com/mlt/select.url?eid=2-s2.0-0034507010&selection=ref&src=s&origin=recordpageen_HK
dc.identifier.volume10en_HK
dc.identifier.issue8en_HK
dc.identifier.spage1413en_HK
dc.identifier.epage1425en_HK
dc.publisher.placeUnited Statesen_HK
dc.identifier.scopusauthoridLeung, KK=35779695300en_HK
dc.identifier.scopusauthoridYung, NHC=7003473369en_HK
dc.identifier.scopusauthoridCheung, PYS=7202595335en_HK

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