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Article: Correlation between hot-carrier-induced interface states and GIDL current increase in N-MOSFET's

TitleCorrelation between hot-carrier-induced interface states and GIDL current increase in N-MOSFET's
Authors
Issue Date1998
PublisherI E E E. The Journal's web site is located at http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=16
Citation
Ieee Transactions On Electron Devices, 1998, v. 45 n. 2, p. 521-528 How to Cite?
AbstractCorrelation between created interface states and GIDL current increase in n-MOSFET's during hot-carrier stress is quantitatively discussed. A trap-assisted two-step tunneling model is used to relate the increased interface-state density (ADH) with the shift in GIDL current (ΔI d). Results show that under appropriate drain-gate biases, the two-step tunneling is so dominant that A/d is insensitive to temperatures up to about 50 °C. With the help of 2-D device simulation, the locations of the drain region with significant two-step tunneling and the energy levels of the traps involved can be found, with both depending on the drain voltage. From these insights on ADit,A/d and their relation, A Du near the midgap can be estimated, with an error less than 10% as compared to the results of chargepumping measurement on the same transistors. Devices with nitrided gate oxide, different gate-oxide thicknesses and different channel dimensions are also tested to verify the above correlation. © 1998 IEEE.
Persistent Identifierhttp://hdl.handle.net/10722/42764
ISSN
2023 Impact Factor: 2.9
2023 SCImago Journal Rankings: 0.785
ISI Accession Number ID
References

 

DC FieldValueLanguage
dc.contributor.authorLai, PTen_HK
dc.contributor.authorXu, JPen_HK
dc.contributor.authorWong, WMen_HK
dc.contributor.authorLo, HBen_HK
dc.contributor.authorCheng, YCen_HK
dc.date.accessioned2007-03-23T04:31:43Z-
dc.date.available2007-03-23T04:31:43Z-
dc.date.issued1998en_HK
dc.identifier.citationIeee Transactions On Electron Devices, 1998, v. 45 n. 2, p. 521-528en_HK
dc.identifier.issn0018-9383en_HK
dc.identifier.urihttp://hdl.handle.net/10722/42764-
dc.description.abstractCorrelation between created interface states and GIDL current increase in n-MOSFET's during hot-carrier stress is quantitatively discussed. A trap-assisted two-step tunneling model is used to relate the increased interface-state density (ADH) with the shift in GIDL current (ΔI d). Results show that under appropriate drain-gate biases, the two-step tunneling is so dominant that A/d is insensitive to temperatures up to about 50 °C. With the help of 2-D device simulation, the locations of the drain region with significant two-step tunneling and the energy levels of the traps involved can be found, with both depending on the drain voltage. From these insights on ADit,A/d and their relation, A Du near the midgap can be estimated, with an error less than 10% as compared to the results of chargepumping measurement on the same transistors. Devices with nitrided gate oxide, different gate-oxide thicknesses and different channel dimensions are also tested to verify the above correlation. © 1998 IEEE.en_HK
dc.format.extent176515 bytes-
dc.format.extent27648 bytes-
dc.format.mimetypeapplication/pdf-
dc.format.mimetypeapplication/msword-
dc.languageengen_HK
dc.publisherI E E E. The Journal's web site is located at http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=16en_HK
dc.relation.ispartofIEEE Transactions on Electron Devicesen_HK
dc.rights©1998 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.-
dc.titleCorrelation between hot-carrier-induced interface states and GIDL current increase in N-MOSFET'sen_HK
dc.typeArticleen_HK
dc.identifier.openurlhttp://library.hku.hk:4550/resserv?sid=HKU:IR&issn=0018-9383&volume=45&issue=2&spage=521&epage=528&date=1998&atitle=Correlation+between+hot-carrier-induced+interface+states+and+GIDL+current+increase+in+n-MOSFET%27sen_HK
dc.identifier.emailLai, PT:laip@eee.hku.hken_HK
dc.identifier.authorityLai, PT=rp00130en_HK
dc.description.naturepublished_or_final_versionen_HK
dc.identifier.doi10.1109/16.658689en_HK
dc.identifier.scopuseid_2-s2.0-0032000296en_HK
dc.identifier.hkuros33981-
dc.relation.referenceshttp://www.scopus.com/mlt/select.url?eid=2-s2.0-0032000296&selection=ref&src=s&origin=recordpageen_HK
dc.identifier.volume45en_HK
dc.identifier.issue2en_HK
dc.identifier.spage521en_HK
dc.identifier.epage528en_HK
dc.identifier.isiWOS:000071692800024-
dc.publisher.placeUnited Statesen_HK
dc.identifier.scopusauthoridLai, PT=7202946460en_HK
dc.identifier.scopusauthoridXu, JP=54681474400en_HK
dc.identifier.scopusauthoridWong, WM=36847948700en_HK
dc.identifier.scopusauthoridLo, HB=7202085394en_HK
dc.identifier.scopusauthoridCheng, YC=27167728600en_HK
dc.identifier.issnl0018-9383-

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