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Article: Planar HTS device process using ion implantation

TitlePlanar HTS device process using ion implantation
Authors
Issue Date1997
PublisherIEEE.
Citation
IEEE Transactions on Applied Superconductivity, 1997, v. 7 n. 2, p. 2713-2718 How to Cite?
AbstractA planar inhibiting fabrication technique of HTS electronic devices has been developed in recent years and is summarized. A systematic study of the properties of ion inhibited HTS films is presented. The inhibition of superconductivity is carried out by the implantation of reactive ions such as Al, B, Ca, and Si into YBCO epitaxial films. The inhibited films are characterized using resistivity, susceptibility, SIMS, XRD, XPS, and SEM measurements. The results indicate that the implanted ions react strongly with oxygen, which turn the films resistive, and even insulative without altering the overall crystalline structure of the films. The effect of ion diffusion is also investigated. Ion gettering phenomenon is observed in Si implanted films. Those effects define the pattern resolution of the planar inhibiting fabrication process. The ion implantation process is applied to the fabrication of HTS single layer devices. These devices include Josephson junctions, DC SQUIDs, RF coils, and microwave waveguides. Operational step-edge junctions and DC SQUIDs with a minimum width of 2 μm were formed and tested at 77 K. Passive devices such as low loss waveguides (1-25 GHz) and high Q resonators (33 MHz) were demonstrated. The performance of these devices, in general, is better than or at least equal to that of dry etched devices. However, the new process offers two major advantages. first, the patterned device is planar, which allows a multilayer device to be built, and second, there is little or no chemical contamination of the patterned devices. To demonstrate the viability of this technique for the fabrication of multilayer devices, simple YBCO/STO/YBCO tri-layer structures (such as crossover and a parallel-plate capacitor), with two implantations were fabricated.
Persistent Identifierhttp://hdl.handle.net/10722/42738
ISSN
2015 Impact Factor: 1.092
2015 SCImago Journal Rankings: 0.381
ISI Accession Number ID

 

DC FieldValueLanguage
dc.contributor.authorMa, Qen_HK
dc.date.accessioned2007-03-23T04:31:13Z-
dc.date.available2007-03-23T04:31:13Z-
dc.date.issued1997en_HK
dc.identifier.citationIEEE Transactions on Applied Superconductivity, 1997, v. 7 n. 2, p. 2713-2718en_HK
dc.identifier.issn1051-8223en_HK
dc.identifier.urihttp://hdl.handle.net/10722/42738-
dc.description.abstractA planar inhibiting fabrication technique of HTS electronic devices has been developed in recent years and is summarized. A systematic study of the properties of ion inhibited HTS films is presented. The inhibition of superconductivity is carried out by the implantation of reactive ions such as Al, B, Ca, and Si into YBCO epitaxial films. The inhibited films are characterized using resistivity, susceptibility, SIMS, XRD, XPS, and SEM measurements. The results indicate that the implanted ions react strongly with oxygen, which turn the films resistive, and even insulative without altering the overall crystalline structure of the films. The effect of ion diffusion is also investigated. Ion gettering phenomenon is observed in Si implanted films. Those effects define the pattern resolution of the planar inhibiting fabrication process. The ion implantation process is applied to the fabrication of HTS single layer devices. These devices include Josephson junctions, DC SQUIDs, RF coils, and microwave waveguides. Operational step-edge junctions and DC SQUIDs with a minimum width of 2 μm were formed and tested at 77 K. Passive devices such as low loss waveguides (1-25 GHz) and high Q resonators (33 MHz) were demonstrated. The performance of these devices, in general, is better than or at least equal to that of dry etched devices. However, the new process offers two major advantages. first, the patterned device is planar, which allows a multilayer device to be built, and second, there is little or no chemical contamination of the patterned devices. To demonstrate the viability of this technique for the fabrication of multilayer devices, simple YBCO/STO/YBCO tri-layer structures (such as crossover and a parallel-plate capacitor), with two implantations were fabricated.en_HK
dc.format.extent865565 bytes-
dc.format.extent25600 bytes-
dc.format.mimetypeapplication/pdf-
dc.format.mimetypeapplication/msword-
dc.languageengen_HK
dc.publisherIEEE.en_HK
dc.rightsCreative Commons: Attribution 3.0 Hong Kong License-
dc.rights©1997 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.en_HK
dc.titlePlanar HTS device process using ion implantationen_HK
dc.typeArticleen_HK
dc.identifier.openurlhttp://library.hku.hk:4550/resserv?sid=HKU:IR&issn=1051-8223&volume=7&issue=2&spage=2713&epage=2718&date=1997&atitle=Planar+HTS+device+process+using+ion+implantationen_HK
dc.description.naturepublished_or_final_versionen_HK
dc.identifier.doi10.1109/77.621798en_HK
dc.identifier.hkuros26530-
dc.identifier.isiWOS:A1997XH86700108-

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