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Article: The design and multiplier-less realization of software radio receivers with reduced system delay

TitleThe design and multiplier-less realization of software radio receivers with reduced system delay
Authors
KeywordsDesign and multiplier-less realization
Low delay
Passband linear-phase finite-impulse response (FIR) and allpass filters
Sampling rate conversion
Semidefinite programming (SDP)
Software radio receiver (SRR)
Variable digital filters (VDF)
Issue Date2004
PublisherIEEE.
Citation
Ieee Transactions On Circuits And Systems I: Regular Papers, 2004, v. 51 n. 12, p. 2444-2459 How to Cite?
AbstractThis paper studies the design and multiplier-less realization of a new software radio receiver (SRR) with reduced system delay. It employs low-delay finite-impulse response (FIR) and digital allpass filters to effectively reduce the system delay of the multistage decimators in SRRs. The optimal least-square and minimax designs of these low-delay FIR and allpass-based filters are formulated as a semidefinite programming (SDP) problem, which allows zero magnitude constraint at ω = π to be incorporated readily as additional linear matrix inequalities (LMIs). By implementing the sampling rate converter (SRC) using a variable digital filter (VDF) immediately after the integer decimators, the needs for an expensive programmable FIR filter in the traditional SRR is avoided. A new method for the optimal minimax design of this VDF-based SRC using SDP is also proposed and compared with traditional weight least squares method. Other implementation issues including the multiplier-less and digital signal processor (DSP) realizations of the SRR and the generation of the clock signal in the SRC are also studied. Design results show that the system delay and implementation complexities (especially in terms of high-speed variable multipliers) of the proposed architecture are considerably reduced as compared with conventional approaches. © 2004 IEEE.
Persistent Identifierhttp://hdl.handle.net/10722/42702
ISSN
2006 Impact Factor: 1.139
2006 SCImago Journal Rankings: 1.111
ISI Accession Number ID
References

 

DC FieldValueLanguage
dc.contributor.authorYeung, KSen_HK
dc.contributor.authorChan, SCen_HK
dc.date.accessioned2007-03-23T04:30:27Z-
dc.date.available2007-03-23T04:30:27Z-
dc.date.issued2004en_HK
dc.identifier.citationIeee Transactions On Circuits And Systems I: Regular Papers, 2004, v. 51 n. 12, p. 2444-2459en_HK
dc.identifier.issn1057-7122en_HK
dc.identifier.urihttp://hdl.handle.net/10722/42702-
dc.description.abstractThis paper studies the design and multiplier-less realization of a new software radio receiver (SRR) with reduced system delay. It employs low-delay finite-impulse response (FIR) and digital allpass filters to effectively reduce the system delay of the multistage decimators in SRRs. The optimal least-square and minimax designs of these low-delay FIR and allpass-based filters are formulated as a semidefinite programming (SDP) problem, which allows zero magnitude constraint at ω = π to be incorporated readily as additional linear matrix inequalities (LMIs). By implementing the sampling rate converter (SRC) using a variable digital filter (VDF) immediately after the integer decimators, the needs for an expensive programmable FIR filter in the traditional SRR is avoided. A new method for the optimal minimax design of this VDF-based SRC using SDP is also proposed and compared with traditional weight least squares method. Other implementation issues including the multiplier-less and digital signal processor (DSP) realizations of the SRR and the generation of the clock signal in the SRC are also studied. Design results show that the system delay and implementation complexities (especially in terms of high-speed variable multipliers) of the proposed architecture are considerably reduced as compared with conventional approaches. © 2004 IEEE.en_HK
dc.format.extent2377497 bytes-
dc.format.extent28672 bytes-
dc.format.mimetypeapplication/pdf-
dc.format.mimetypeapplication/msword-
dc.languageengen_HK
dc.publisherIEEE.en_HK
dc.relation.ispartofIEEE Transactions on Circuits and Systems I: Regular Papersen_HK
dc.rightsCreative Commons: Attribution 3.0 Hong Kong License-
dc.rights©2004 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.en_HK
dc.subjectDesign and multiplier-less realizationen_HK
dc.subjectLow delayen_HK
dc.subjectPassband linear-phase finite-impulse response (FIR) and allpass filtersen_HK
dc.subjectSampling rate conversionen_HK
dc.subjectSemidefinite programming (SDP)en_HK
dc.subjectSoftware radio receiver (SRR)en_HK
dc.subjectVariable digital filters (VDF)en_HK
dc.titleThe design and multiplier-less realization of software radio receivers with reduced system delayen_HK
dc.typeArticleen_HK
dc.identifier.openurlhttp://library.hku.hk:4550/resserv?sid=HKU:IR&issn=1549-8328&volume=51&issue=12&spage=2444&epage=2459&date=2004&atitle=The+design+and+multiplier-less+realization+of+software+radio+receivers+with+reduced+system+delayen_HK
dc.identifier.emailChan, SC:scchan@eee.hku.hken_HK
dc.identifier.authorityChan, SC=rp00094en_HK
dc.description.naturepublished_or_final_versionen_HK
dc.identifier.doi10.1109/TCSI.2004.838253en_HK
dc.identifier.scopuseid_2-s2.0-10944262673en_HK
dc.identifier.hkuros102820-
dc.relation.referenceshttp://www.scopus.com/mlt/select.url?eid=2-s2.0-10944262673&selection=ref&src=s&origin=recordpageen_HK
dc.identifier.volume51en_HK
dc.identifier.issue12en_HK
dc.identifier.spage2444en_HK
dc.identifier.epage2459en_HK
dc.identifier.isiWOS:000225484600011-
dc.publisher.placeUnited Statesen_HK
dc.identifier.scopusauthoridYeung, KS=7202425050en_HK
dc.identifier.scopusauthoridChan, SC=13310287100en_HK

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