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Article: Standard cell layout with regular contact placement

TitleStandard cell layout with regular contact placement
Authors
KeywordsDouble exposure
Fabrication-friendly layout
Low k1 lithography
Regularly placed contact
RETs
Standard cells
Issue Date2004
PublisherIEEE.
Citation
Ieee Transactions On Semiconductor Manufacturing, 2004, v. 17 n. 3, p. 375-383 How to Cite?
AbstractThe practicability and methodology of applying regularly placed contacts on layout design of standard cells are studied. The regular placement enables more effective use of resolution enhancement technologies, which in turn allows for a reduction of critical dimensions. Although placing contacts on a grid adds restrictions during cell layout, overall circuit area can be made smaller by a careful selection of the grid pitch, allowing slight contact offset, applying double exposure, and shrinking the minimum size and pitch. The contact level of 250 nm standard cells was shrunk by 10%, resulting in an area change ranging from -20% to +25% with an average decrease of 5% for the 84 cells studied. The areas of two circuits, a finite-impulse-response (FIR) filter and an add-compare-select (ACS) unit in the Viterbi decoder, decrease by 4% and 2%, respectively.
Persistent Identifierhttp://hdl.handle.net/10722/42686
ISSN
2015 Impact Factor: 1.045
2015 SCImago Journal Rankings: 0.640
ISI Accession Number ID
References

 

DC FieldValueLanguage
dc.contributor.authorWang, Jen_HK
dc.contributor.authorWong, AKen_HK
dc.contributor.authorLam, EYen_HK
dc.date.accessioned2007-03-23T04:30:05Z-
dc.date.available2007-03-23T04:30:05Z-
dc.date.issued2004en_HK
dc.identifier.citationIeee Transactions On Semiconductor Manufacturing, 2004, v. 17 n. 3, p. 375-383en_HK
dc.identifier.issn0894-6507en_HK
dc.identifier.urihttp://hdl.handle.net/10722/42686-
dc.description.abstractThe practicability and methodology of applying regularly placed contacts on layout design of standard cells are studied. The regular placement enables more effective use of resolution enhancement technologies, which in turn allows for a reduction of critical dimensions. Although placing contacts on a grid adds restrictions during cell layout, overall circuit area can be made smaller by a careful selection of the grid pitch, allowing slight contact offset, applying double exposure, and shrinking the minimum size and pitch. The contact level of 250 nm standard cells was shrunk by 10%, resulting in an area change ranging from -20% to +25% with an average decrease of 5% for the 84 cells studied. The areas of two circuits, a finite-impulse-response (FIR) filter and an add-compare-select (ACS) unit in the Viterbi decoder, decrease by 4% and 2%, respectively.en_HK
dc.format.extent1529695 bytes-
dc.format.extent25600 bytes-
dc.format.mimetypeapplication/pdf-
dc.format.mimetypeapplication/msword-
dc.languageengen_HK
dc.publisherIEEE.en_HK
dc.relation.ispartofIEEE Transactions on Semiconductor Manufacturingen_HK
dc.rightsCreative Commons: Attribution 3.0 Hong Kong License-
dc.rights©2004 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.en_HK
dc.subjectDouble exposureen_HK
dc.subjectFabrication-friendly layouten_HK
dc.subjectLow k1 lithographyen_HK
dc.subjectRegularly placed contacten_HK
dc.subjectRETsen_HK
dc.subjectStandard cellsen_HK
dc.titleStandard cell layout with regular contact placementen_HK
dc.typeArticleen_HK
dc.identifier.openurlhttp://library.hku.hk:4550/resserv?sid=HKU:IR&issn=0894-6507&volume=17&issue=3&spage=375&epage=383&date=2004&atitle=Standard+cell+layout+with+regular+contact+placementen_HK
dc.identifier.emailLam, EY:elam@eee.hku.hken_HK
dc.identifier.authorityLam, EY=rp00131en_HK
dc.description.naturepublished_or_final_versionen_HK
dc.identifier.doi10.1109/TSM.2004.831522en_HK
dc.identifier.scopuseid_2-s2.0-4344694445en_HK
dc.identifier.hkuros101032-
dc.relation.referenceshttp://www.scopus.com/mlt/select.url?eid=2-s2.0-4344694445&selection=ref&src=s&origin=recordpageen_HK
dc.identifier.volume17en_HK
dc.identifier.issue3en_HK
dc.identifier.spage375en_HK
dc.identifier.epage383en_HK
dc.identifier.isiWOS:000223187900019-
dc.publisher.placeUnited Statesen_HK
dc.identifier.scopusauthoridWang, J=8716933500en_HK
dc.identifier.scopusauthoridWong, AK=7403147663en_HK
dc.identifier.scopusauthoridLam, EY=7102890004en_HK

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