Showing results 1 to 9 of 9
| Title | Author(s) | Issue Date | Views | |
|---|---|---|---|---|
A faster approximation scheme for timing driven minimum cost layer assignment Proceeding/Conference:Proceedings of the International Symposium on Physical Design | 2009 | |||
A fully polynomial time approximation scheme for timing driven minimum cost buffer insertion Proceeding/Conference:Proceedings - Design Automation Conference | 2009 | |||
A fully polynomial-time approximation scheme for timing-constrained minimum cost layer assignment Journal:IEEE Transactions on Circuits and Systems II: Express Briefs | 2009 | |||
A polynomial time approximation scheme for timing constrained minimum cost layer assignment Proceeding/Conference:IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD | 2008 | |||
CATALYST: Planning layer directives for effective design closure Proceeding/Conference:Proceedings -Design, Automation and Test in Europe, DATE | 2013 | |||
Fast algorithms for slew constrained minimum cost buffering Proceeding/Conference:Proceedings - Design Automation Conference | 2006 | |||
Fast algorithms for slew-constrained minimum cost buffering Journal:IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 2007 | |||
Fast interconnect synthesis with layer assignment Proceeding/Conference:Proceedings of the International Symposium on Physical Design | 2008 | |||
Ultra-fast interconnect driven cell cloning for minimizing critical path delay Proceeding/Conference:Proceedings of the International Symposium on Physical Design | 2010 |