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Article: Design of quadruple precision multiplier architectures with SIMD single and double precision support

TitleDesign of quadruple precision multiplier architectures with SIMD single and double precision support
Authors
KeywordsFloating point arithmetic
Multiplier
SIMD
Modified booth multiplier
Karatsuba multiplication
Multi-mode arithmetic
ASIC
Issue Date2019
PublisherElsevier BV. The Journal's web site is located at http://www.elsevier.com/locate/vlsi
Citation
Integration: the VLSI journal, 2019, v. 65, p. 163-174 How to Cite?
AbstractThis paper proposes architectures for dual-mode and tri-mode dynamically configurable multiplier for quadruple precision arithmetic. The proposed dual-mode QPdDP multiplier architectures can either compute on a pair of quadruple precision (QP) operands or provide SIMD support for two-parallel (dual) sets of double precision (DP) operands. The proposed tri-mode QPdDPqSP multiplier architectures are aimed to include the four-parallel (quad) single precision (SP) along with dual-DP and a QP operand processing. For the underlying largest sub-component, the mantissa multiplier, two methods are analyzed to design the dual-mode/tri-mode architectures. One is based on the Karatsuba method, and in another a dual-mode/tri-mode Radix-4 Modified Booth (MB) multiplier is proposed. The proposed dual-mode/tri-mode MB multiplier requires few extra 2:1 MUXs as an overhead compared to a simple MB multiplier. To support dual-mode/tri-mode functioning other important sub-components of the FP multiplication are also re-designed for multi-mode support. The proposed architectures are synthesized using UMC 90 nm ASIC technology, and are compared against prior literature in terms of area, period, and a unified metric “Area (Gate Count) × Period (FO4) × Latency × Throughput (in cycles)”. The dual-mode/tri-mode FP architectures with MB mantissa multipliers shows better timings, however, those with Karatsuba mantissa multipliers acquires smaller area.
Persistent Identifierhttp://hdl.handle.net/10722/275725
ISSN
2017 Impact Factor: 0.906
2015 SCImago Journal Rankings: 0.283
ISI Accession Number ID

 

DC FieldValueLanguage
dc.contributor.authorJaiswal, MK-
dc.contributor.authorSo, HKH-
dc.date.accessioned2019-09-10T02:48:25Z-
dc.date.available2019-09-10T02:48:25Z-
dc.date.issued2019-
dc.identifier.citationIntegration: the VLSI journal, 2019, v. 65, p. 163-174-
dc.identifier.issn0167-9260-
dc.identifier.urihttp://hdl.handle.net/10722/275725-
dc.description.abstractThis paper proposes architectures for dual-mode and tri-mode dynamically configurable multiplier for quadruple precision arithmetic. The proposed dual-mode QPdDP multiplier architectures can either compute on a pair of quadruple precision (QP) operands or provide SIMD support for two-parallel (dual) sets of double precision (DP) operands. The proposed tri-mode QPdDPqSP multiplier architectures are aimed to include the four-parallel (quad) single precision (SP) along with dual-DP and a QP operand processing. For the underlying largest sub-component, the mantissa multiplier, two methods are analyzed to design the dual-mode/tri-mode architectures. One is based on the Karatsuba method, and in another a dual-mode/tri-mode Radix-4 Modified Booth (MB) multiplier is proposed. The proposed dual-mode/tri-mode MB multiplier requires few extra 2:1 MUXs as an overhead compared to a simple MB multiplier. To support dual-mode/tri-mode functioning other important sub-components of the FP multiplication are also re-designed for multi-mode support. The proposed architectures are synthesized using UMC 90 nm ASIC technology, and are compared against prior literature in terms of area, period, and a unified metric “Area (Gate Count) × Period (FO4) × Latency × Throughput (in cycles)”. The dual-mode/tri-mode FP architectures with MB mantissa multipliers shows better timings, however, those with Karatsuba mantissa multipliers acquires smaller area.-
dc.languageeng-
dc.publisherElsevier BV. The Journal's web site is located at http://www.elsevier.com/locate/vlsi-
dc.relation.ispartofIntegration: the VLSI journal-
dc.subjectFloating point arithmetic-
dc.subjectMultiplier-
dc.subjectSIMD-
dc.subjectModified booth multiplier-
dc.subjectKaratsuba multiplication-
dc.subjectMulti-mode arithmetic-
dc.subjectASIC-
dc.titleDesign of quadruple precision multiplier architectures with SIMD single and double precision support-
dc.typeArticle-
dc.identifier.emailJaiswal, MK: manishkj@hku.hk-
dc.identifier.emailSo, HKH: hso@eee.hku.hk-
dc.identifier.authoritySo, HKH=rp00169-
dc.description.naturelink_to_subscribed_fulltext-
dc.identifier.doi10.1016/j.vlsi.2018.12.002-
dc.identifier.scopuseid_2-s2.0-85058814108-
dc.identifier.hkuros304142-
dc.identifier.volume65-
dc.identifier.spage163-
dc.identifier.epage174-
dc.identifier.isiWOS:000474316700015-
dc.publisher.placeNetherlands-

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