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Conference Paper: Ultra-low latency continuous block-parallel stream windowing using FPGA on-chip memory

TitleUltra-low latency continuous block-parallel stream windowing using FPGA on-chip memory
Authors
Issue Date2017
PublisherIEEE Computer Society. The Journal's web site is located at http://ieeexplore.ieee.org/xpl/conhome.jsp?punumber=1000290
Citation
Proceedings of 2017 International Conference on Field Programmable Technology (ICFPT), Melbourne, VIC, Australia, 11-13 December 2017, p. 56-63 How to Cite?
AbstractIn this paper, we propose and demonstrate a real-time ultra-fast multi-data stream processing methodology on FPGA called “SWIM” (Stream Windowing on Interleaved Memory). The method exploits the flexible on-chip block memory fabric on existing FPGA architectures to achieve ultra-low-latency and fully pipelined continuous data flow while maintaining linear spatial locality of data for efficient data addressing and processing. The SWIM method is directly applicable to many practical applications such as real-time stencil computing, streaming image data processing, as well as closed loop-control systems that require ultra-low latency interleaved access and processing of high-speed sensor data. We demonstrate two practical cases on actual FPGA for generic 3-by-3 2-D convolution filter and image super-resolution method using pixel interleaving. Both memory usage and latency scales linearly with window height, or width of the 2-D input data set. The generic implementation of SWIM on FPGA showed impressive worst-case operation frequency of 410 MHz and uses 9.0χ and 5.6χ less Register and LUT resources respectively compared with a high-level synthesis solution.
Persistent Identifierhttp://hdl.handle.net/10722/263553

 

DC FieldValueLanguage
dc.contributor.authorWong, JS-
dc.contributor.authorShi, R-
dc.contributor.authorWang, M-
dc.contributor.authorSo, HKH-
dc.date.accessioned2018-10-22T07:40:48Z-
dc.date.available2018-10-22T07:40:48Z-
dc.date.issued2017-
dc.identifier.citationProceedings of 2017 International Conference on Field Programmable Technology (ICFPT), Melbourne, VIC, Australia, 11-13 December 2017, p. 56-63-
dc.identifier.urihttp://hdl.handle.net/10722/263553-
dc.description.abstractIn this paper, we propose and demonstrate a real-time ultra-fast multi-data stream processing methodology on FPGA called “SWIM” (Stream Windowing on Interleaved Memory). The method exploits the flexible on-chip block memory fabric on existing FPGA architectures to achieve ultra-low-latency and fully pipelined continuous data flow while maintaining linear spatial locality of data for efficient data addressing and processing. The SWIM method is directly applicable to many practical applications such as real-time stencil computing, streaming image data processing, as well as closed loop-control systems that require ultra-low latency interleaved access and processing of high-speed sensor data. We demonstrate two practical cases on actual FPGA for generic 3-by-3 2-D convolution filter and image super-resolution method using pixel interleaving. Both memory usage and latency scales linearly with window height, or width of the 2-D input data set. The generic implementation of SWIM on FPGA showed impressive worst-case operation frequency of 410 MHz and uses 9.0χ and 5.6χ less Register and LUT resources respectively compared with a high-level synthesis solution.-
dc.languageeng-
dc.publisherIEEE Computer Society. The Journal's web site is located at http://ieeexplore.ieee.org/xpl/conhome.jsp?punumber=1000290-
dc.relation.ispartofInternational Conference on FieId Programmable Technology Proceedings-
dc.rightsInternational Conference on FieId Programmable Technology Proceedings. Copyright © IEEE Computer Society.-
dc.titleUltra-low latency continuous block-parallel stream windowing using FPGA on-chip memory-
dc.typeConference_Paper-
dc.identifier.emailWong, JS: jsjwong@hku.hk-
dc.identifier.emailSo, HKH: hso@eee.hku.hk-
dc.identifier.authoritySo, HKH=rp00169-
dc.identifier.doi10.1109/FPT.2017.8280121-
dc.identifier.hkuros295132-
dc.identifier.spage56-
dc.identifier.epage63-
dc.publisher.placeUnited States-

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