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Conference Paper: Universal number posit arithmetic generator on FPGA

TitleUniversal number posit arithmetic generator on FPGA
Authors
Issue Date2018
PublisherIEEE Computer Society. The Journal's web site is located at http://ieeexplore.ieee.org/xpl/conhome.jsp?punumber=1000198
Citation
Proceedings of 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE), Dresden, Germany, 19-23 March 2018, p. 1159-1162 How to Cite?
AbstractPosit number system format includes a run-time varying exponent component, defined by a combination of regime-bit (with run-time varying length) and exponent-bit (with size of up to ES bits, the exponent size). This also leads to a run-time variation in its mantissa field size and position. This run-time variation in posit format poses a hardware design challenge. Being a recent development, posit lacks for its adequate hardware arithmetic architectures. Thus, this paper is aimed towards the posit arithmetic algorithmic development and their generic hardware generator. It is focused on basic posit arithmetic (floating-point to posit conversion, posit to floating point conversion, addition/subtraction and multiplication). These are also demonstrated on a FPGA platform. Target is to develop an open-source solution for generating basic posit arithmetic architectures with parameterized choices. This contribution would enable further exploration and evaluation of posit system.
Persistent Identifierhttp://hdl.handle.net/10722/263549
ISSN

 

DC FieldValueLanguage
dc.contributor.authorJaiswal, MK-
dc.contributor.authorSo, HKH-
dc.date.accessioned2018-10-22T07:40:44Z-
dc.date.available2018-10-22T07:40:44Z-
dc.date.issued2018-
dc.identifier.citationProceedings of 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE), Dresden, Germany, 19-23 March 2018, p. 1159-1162-
dc.identifier.issn1530-1591-
dc.identifier.urihttp://hdl.handle.net/10722/263549-
dc.description.abstractPosit number system format includes a run-time varying exponent component, defined by a combination of regime-bit (with run-time varying length) and exponent-bit (with size of up to ES bits, the exponent size). This also leads to a run-time variation in its mantissa field size and position. This run-time variation in posit format poses a hardware design challenge. Being a recent development, posit lacks for its adequate hardware arithmetic architectures. Thus, this paper is aimed towards the posit arithmetic algorithmic development and their generic hardware generator. It is focused on basic posit arithmetic (floating-point to posit conversion, posit to floating point conversion, addition/subtraction and multiplication). These are also demonstrated on a FPGA platform. Target is to develop an open-source solution for generating basic posit arithmetic architectures with parameterized choices. This contribution would enable further exploration and evaluation of posit system.-
dc.languageeng-
dc.publisherIEEE Computer Society. The Journal's web site is located at http://ieeexplore.ieee.org/xpl/conhome.jsp?punumber=1000198-
dc.relation.ispartofDesign, Automation, and Test in Europe Conference and Exhibition Proceedings-
dc.rightsDesign, Automation, and Test in Europe Conference and Exhibition Proceedings. Copyright © IEEE Computer Society.-
dc.titleUniversal number posit arithmetic generator on FPGA-
dc.typeConference_Paper-
dc.identifier.emailJaiswal, MK: manishkj@hku.hk-
dc.identifier.emailSo, HKH: hso@eee.hku.hk-
dc.identifier.authoritySo, HKH=rp00169-
dc.identifier.doi10.23919/DATE.2018.8342187-
dc.identifier.hkuros294458-
dc.identifier.spage1159-
dc.identifier.epage1162-
dc.publisher.placeUnited States-

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