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Conference Paper: A soft processor overlay with tightly-coupled FPGA accelerator

TitleA soft processor overlay with tightly-coupled FPGA accelerator
Authors
Issue Date2016
Citation
The 2nd International Workshop on Overlay Architectures for FPGAs (OLAF2016), Monterey, CA., 21 Febreuary 2016. In Conference Proceedings, 2016, p. 31-36 How to Cite?
AbstractFPGA overlays are commonly implemented as coarse-grained reconfigurable architectures with a goal to improve designers’ productivity through balancing flexibility and ease of configuration of the underlying fabric. To truly facilitate full application acceleration, it is often necessary to also include a highly efficient processor that integrates and collaborates with the accelerators while maintaining the benefits of being implemented within the same overlay framework. This paper presents an open-source soft processor that is designed to tightly-couple with FPGA accelerators as part of an overlay framework. RISC-V is chosen as the instruction set for its openness and portability, and the soft processor is designed as a 4-stage pipeline to balance resource consumption and performance when implemented on FPGAs. The processor is generically implemented so as to promote design portability and compatibility across different FPGA platforms. Experimental results show that integrated software-hardware applications using the proposed tightly-coupled architecture achieve comparable performance as hardware-only accelerators while the proposed architecture provides additional run-time flexibility. The processor has been synthesized to both low-end and high-performance FPGA families from different vendors, achieving the highest frequency of 268:67MHz and resource consumption comparable to existing RISC-V designs.
Persistent Identifierhttp://hdl.handle.net/10722/234981

 

DC FieldValueLanguage
dc.contributor.authorNg, HC-
dc.contributor.authorLiu, C-
dc.contributor.authorSo, HKH-
dc.date.accessioned2016-10-14T13:50:31Z-
dc.date.available2016-10-14T13:50:31Z-
dc.date.issued2016-
dc.identifier.citationThe 2nd International Workshop on Overlay Architectures for FPGAs (OLAF2016), Monterey, CA., 21 Febreuary 2016. In Conference Proceedings, 2016, p. 31-36-
dc.identifier.urihttp://hdl.handle.net/10722/234981-
dc.description.abstractFPGA overlays are commonly implemented as coarse-grained reconfigurable architectures with a goal to improve designers’ productivity through balancing flexibility and ease of configuration of the underlying fabric. To truly facilitate full application acceleration, it is often necessary to also include a highly efficient processor that integrates and collaborates with the accelerators while maintaining the benefits of being implemented within the same overlay framework. This paper presents an open-source soft processor that is designed to tightly-couple with FPGA accelerators as part of an overlay framework. RISC-V is chosen as the instruction set for its openness and portability, and the soft processor is designed as a 4-stage pipeline to balance resource consumption and performance when implemented on FPGAs. The processor is generically implemented so as to promote design portability and compatibility across different FPGA platforms. Experimental results show that integrated software-hardware applications using the proposed tightly-coupled architecture achieve comparable performance as hardware-only accelerators while the proposed architecture provides additional run-time flexibility. The processor has been synthesized to both low-end and high-performance FPGA families from different vendors, achieving the highest frequency of 268:67MHz and resource consumption comparable to existing RISC-V designs.-
dc.languageeng-
dc.relation.ispartofInternational Workshop on Overlay Architectures for FPGAs, OLAF 2016-
dc.rightsCreative Commons: Attribution 3.0 Hong Kong License-
dc.rightsAuthor holds the copyright-
dc.titleA soft processor overlay with tightly-coupled FPGA accelerator-
dc.typeConference_Paper-
dc.identifier.emailSo, HKH: hso@eee.hku.hk-
dc.identifier.authoritySo, HKH=rp00169-
dc.description.naturepostprint-
dc.identifier.hkuros268686-
dc.identifier.spage31-
dc.identifier.epage36-
dc.customcontrol.immutablesml 161202-

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