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Article: Effects of thermal annealing on La2O3 gate dielectric of InGaZnO thin-film transistor

TitleEffects of thermal annealing on La2O3 gate dielectric of InGaZnO thin-film transistor
Authors
Issue Date2015
PublisherElectrochemical Society, Inc. The Journal's web site is located at http://ssl.ecsdl.org/
Citation
ECS Solid State Letters, 2015, v. 4 n. 9, p. Q44-Q46 How to Cite?
AbstractThe effects of thermal annealing on La2O3 gate dielectric of InGaZnO thin-film transistor (TFT) are investigated by varying annealing temperature. Due to densification and enhanced moisture resistance of the La2O3 film, its surface roughness and interface with InGaZnO are improved by the thermal annealing, thus leading to significant improvement in the TFT electrical performance. However, higher-temperature (450 oC) annealing deteriorates the dielectric roughness and induces more traps associated with grain boundaries in the La2O3 film. The TFT with an appropriate annealing (350 oC) shows the best performance with smallest sub-threshold swing (0.276 V/dec), lowest threshold voltage (3.01 V), highest field-effect mobility (23.2 cm2/V.s) and largest on-off current ratio (3.52×108). © 2015 The Electrochemical Society.
Persistent Identifierhttp://hdl.handle.net/10722/234050
ISSN
2015 Impact Factor: 1.142
2015 SCImago Journal Rankings: 0.559

 

DC FieldValueLanguage
dc.contributor.authorHuang, XD-
dc.contributor.authorSong, J-
dc.contributor.authorLai, PT-
dc.date.accessioned2016-10-14T06:58:44Z-
dc.date.available2016-10-14T06:58:44Z-
dc.date.issued2015-
dc.identifier.citationECS Solid State Letters, 2015, v. 4 n. 9, p. Q44-Q46-
dc.identifier.issn2162-8742-
dc.identifier.urihttp://hdl.handle.net/10722/234050-
dc.description.abstractThe effects of thermal annealing on La2O3 gate dielectric of InGaZnO thin-film transistor (TFT) are investigated by varying annealing temperature. Due to densification and enhanced moisture resistance of the La2O3 film, its surface roughness and interface with InGaZnO are improved by the thermal annealing, thus leading to significant improvement in the TFT electrical performance. However, higher-temperature (450 oC) annealing deteriorates the dielectric roughness and induces more traps associated with grain boundaries in the La2O3 film. The TFT with an appropriate annealing (350 oC) shows the best performance with smallest sub-threshold swing (0.276 V/dec), lowest threshold voltage (3.01 V), highest field-effect mobility (23.2 cm2/V.s) and largest on-off current ratio (3.52×108). © 2015 The Electrochemical Society.-
dc.languageeng-
dc.publisherElectrochemical Society, Inc. The Journal's web site is located at http://ssl.ecsdl.org/-
dc.relation.ispartofECS Solid State Letters-
dc.rightsECS Solid State Letters. Copyright © Electrochemical Society, Inc.-
dc.rightsCreative Commons: Attribution 3.0 Hong Kong License-
dc.titleEffects of thermal annealing on La2O3 gate dielectric of InGaZnO thin-film transistor-
dc.typeArticle-
dc.identifier.emailLai, PT: laip@eee.hku.hk-
dc.identifier.authorityLai, PT=rp00130-
dc.description.naturepostprint-
dc.identifier.doi10.1149/2.0011509ssl-
dc.identifier.scopuseid_2-s2.0-84937540098-
dc.identifier.hkuros267798-
dc.identifier.volume4-
dc.identifier.issue9-
dc.identifier.spageQ44-
dc.identifier.epageQ46-
dc.publisher.placeUnited States-
dc.customcontrol.immutablesml 161108-

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