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Article: Area-Efficient Architecture for Dual-Mode Double Precision Floating Point Division

TitleArea-Efficient Architecture for Dual-Mode Double Precision Floating Point Division
Authors
Issue Date2016
PublisherIEEE.
Citation
IEEE Transactions on Circuits and Systems--I: Regular Papers, , in press How to Cite?
Persistent Identifierhttp://hdl.handle.net/10722/234045

 

DC FieldValueLanguage
dc.contributor.authorJaiswal, MK-
dc.contributor.authorSo, HKH-
dc.date.accessioned2016-10-14T06:58:42Z-
dc.date.available2016-10-14T06:58:42Z-
dc.date.issued2016-
dc.identifier.citationIEEE Transactions on Circuits and Systems--I: Regular Papers, , in press-
dc.identifier.urihttp://hdl.handle.net/10722/234045-
dc.languageeng-
dc.publisherIEEE. -
dc.relation.ispartofIEEE Transactions on Circuits and Systems--I: Regular Papers-
dc.rightsIEEE Transactions on Circuits and Systems--I: Regular Papers. Copyright © IEEE.-
dc.rights©20xx IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. -
dc.titleArea-Efficient Architecture for Dual-Mode Double Precision Floating Point Division-
dc.typeArticle-
dc.identifier.emailJaiswal, MK: manishkj@hku.hk-
dc.identifier.emailSo, HKH: hso@eee.hku.hk-
dc.identifier.authoritySo, HKH=rp00169-
dc.identifier.doi10.1109/TCSI.2016.2607227-
dc.identifier.hkuros267491-
dc.identifier.volumein press-

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