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Article: Area-Efficient Architecture for Dual-Mode Double Precision Floating Point Division

TitleArea-Efficient Architecture for Dual-Mode Double Precision Floating Point Division
Authors
Issue Date2017
PublisherIEEE. The Journal's web site is located at http://tcas1.polito.it/
Citation
IEEE Transactions on Circuits and Systems I: Regular Papers, 2017, v. 64, p. 386-398 How to Cite?
Persistent Identifierhttp://hdl.handle.net/10722/234045
ISSN
2017 Impact Factor: 2.823
2015 SCImago Journal Rankings: 1.394

 

DC FieldValueLanguage
dc.contributor.authorJaiswal, MK-
dc.contributor.authorSo, HKH-
dc.date.accessioned2016-10-14T06:58:42Z-
dc.date.available2016-10-14T06:58:42Z-
dc.date.issued2017-
dc.identifier.citationIEEE Transactions on Circuits and Systems I: Regular Papers, 2017, v. 64, p. 386-398-
dc.identifier.issn1549-8328-
dc.identifier.urihttp://hdl.handle.net/10722/234045-
dc.languageeng-
dc.publisherIEEE. The Journal's web site is located at http://tcas1.polito.it/-
dc.relation.ispartofIEEE Transactions on Circuits and Systems I: Regular Papers-
dc.rightsIEEE Transactions on Circuits and Systems I: Regular Papers. Copyright © IEEE.-
dc.rights©20xx IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.-
dc.titleArea-Efficient Architecture for Dual-Mode Double Precision Floating Point Division-
dc.typeArticle-
dc.identifier.emailJaiswal, MK: manishkj@hku.hk-
dc.identifier.emailSo, HKH: hso@eee.hku.hk-
dc.identifier.authoritySo, HKH=rp00169-
dc.identifier.doi10.1109/TCSI.2016.2607227-
dc.identifier.hkuros280262-
dc.identifier.hkuros267491-
dc.identifier.volume64-
dc.identifier.spage386-
dc.identifier.epage398-
dc.publisher.placeUnited States-

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