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Article: Direct tunnelling gate leakage variability in Nano-CMOS transistors

TitleDirect tunnelling gate leakage variability in Nano-CMOS transistors
Authors
KeywordsDevice variability
gate leakage
direct tunnelling
random dopant fluctuations (RDFs)
oxide thickness fluctuations (OTFs)
Issue Date2010
Citation
IEEE Transactions on Electron Devices, 2010, v. 57, n. 11, p. 3106-3114 How to Cite?
AbstractA comprehensive simulation methodology for the systematic study of gate leakage variability in realistic nanoscale bulk CMOS transistors, on a statistical scale, is presented for the first time. This is based on the Glasgow atomistic 3-D driftdiffusion device simulator with density-gradient quantum corrections, which is capable of modeling various sources of stochastic variability, including random dopant fluctuations (RDFs) and oxide thickness fluctuations (OTFs). The capabilities of the simulator are extended to model direct tunnelling of electrons through the gate dielectric by means of an improved WentzelKramerBrillouin approximation with one model parameter only. The methodology is applied for the detailed study of the gate leakage variability arising from RDFs and OTFs in a 25-nm square-gate n-channel metaloxidesemiconductor field-effect transistor with conventional architecture. The origins of gate leakage variability and gate current increase due to RDFs and OTFs individually, and in combination, are analyzed for bias conditions that are relevant to static power dissipation in digital CMOS circuits. © 2010 IEEE.
Persistent Identifierhttp://hdl.handle.net/10722/221314
ISSN
2015 Impact Factor: 2.207
2015 SCImago Journal Rankings: 1.436

 

DC FieldValueLanguage
dc.contributor.authorMarkov, Stanislav-
dc.contributor.authorRoy, Scott-
dc.contributor.authorAsenov, Asen-
dc.date.accessioned2015-11-18T06:08:58Z-
dc.date.available2015-11-18T06:08:58Z-
dc.date.issued2010-
dc.identifier.citationIEEE Transactions on Electron Devices, 2010, v. 57, n. 11, p. 3106-3114-
dc.identifier.issn0018-9383-
dc.identifier.urihttp://hdl.handle.net/10722/221314-
dc.description.abstractA comprehensive simulation methodology for the systematic study of gate leakage variability in realistic nanoscale bulk CMOS transistors, on a statistical scale, is presented for the first time. This is based on the Glasgow atomistic 3-D driftdiffusion device simulator with density-gradient quantum corrections, which is capable of modeling various sources of stochastic variability, including random dopant fluctuations (RDFs) and oxide thickness fluctuations (OTFs). The capabilities of the simulator are extended to model direct tunnelling of electrons through the gate dielectric by means of an improved WentzelKramerBrillouin approximation with one model parameter only. The methodology is applied for the detailed study of the gate leakage variability arising from RDFs and OTFs in a 25-nm square-gate n-channel metaloxidesemiconductor field-effect transistor with conventional architecture. The origins of gate leakage variability and gate current increase due to RDFs and OTFs individually, and in combination, are analyzed for bias conditions that are relevant to static power dissipation in digital CMOS circuits. © 2010 IEEE.-
dc.languageeng-
dc.relation.ispartofIEEE Transactions on Electron Devices-
dc.subjectDevice variability-
dc.subjectgate leakage-
dc.subjectdirect tunnelling-
dc.subjectrandom dopant fluctuations (RDFs)-
dc.subjectoxide thickness fluctuations (OTFs)-
dc.titleDirect tunnelling gate leakage variability in Nano-CMOS transistors-
dc.typeArticle-
dc.description.natureLink_to_subscribed_fulltext-
dc.identifier.doi10.1109/TED.2010.2075932-
dc.identifier.scopuseid_2-s2.0-78049283302-
dc.identifier.volume57-
dc.identifier.issue11-
dc.identifier.spage3106-
dc.identifier.epage3114-

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