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Conference Paper: A power modelling approach for many-core architectures

TitleA power modelling approach for many-core architectures
Authors
KeywordsMany-core
Power management
Power modelling
Model
Issue Date2014
PublisherIEEE. The Journal's web site is located at http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=6963208
Citation
The 10th International Conference on Semantics, Knowledge and Grids (SKG 2014), Beijing, China, 27-29 August 2014. In Conference Proceedings, 2014, p. 128-132 How to Cite?
AbstractMany-core architectures are playing an important role in the HPC systems. But they are giving high performance at the cost of a great electrical power consumption. On Tianhe-2 supercomputer, the Xeon Phi many-core processors contribute nearly 80% of the system power. Power models are important to guide the design of dynamic power management (DPM) algorithms by predicting the power consumption with respect to power states and program execution patterns. However, the complexity of many-core hardware design makes power modelling be a challenging work. These concerns lead us to try a power modelling approach for many-core architectures based on the performance monitoring counters (PMC). The key insight is based on a large number of micro benchmarks on a real many-core platform, where we find some essential rules determining the chip power. Following the modelling approach, we develop an accurate chip power model for the Intel SCC many-core chip. Experimental comparison shows that our model is much more accurate than others. © 2014 IEEE.
Persistent Identifierhttp://hdl.handle.net/10722/219216
ISBN

 

DC FieldValueLanguage
dc.contributor.authorLai, Z-
dc.contributor.authorLam, KT-
dc.contributor.authorWang, CL-
dc.contributor.authorSu, J-
dc.date.accessioned2015-09-18T07:17:58Z-
dc.date.available2015-09-18T07:17:58Z-
dc.date.issued2014-
dc.identifier.citationThe 10th International Conference on Semantics, Knowledge and Grids (SKG 2014), Beijing, China, 27-29 August 2014. In Conference Proceedings, 2014, p. 128-132-
dc.identifier.isbn978-147996715-5-
dc.identifier.urihttp://hdl.handle.net/10722/219216-
dc.description.abstractMany-core architectures are playing an important role in the HPC systems. But they are giving high performance at the cost of a great electrical power consumption. On Tianhe-2 supercomputer, the Xeon Phi many-core processors contribute nearly 80% of the system power. Power models are important to guide the design of dynamic power management (DPM) algorithms by predicting the power consumption with respect to power states and program execution patterns. However, the complexity of many-core hardware design makes power modelling be a challenging work. These concerns lead us to try a power modelling approach for many-core architectures based on the performance monitoring counters (PMC). The key insight is based on a large number of micro benchmarks on a real many-core platform, where we find some essential rules determining the chip power. Following the modelling approach, we develop an accurate chip power model for the Intel SCC many-core chip. Experimental comparison shows that our model is much more accurate than others. © 2014 IEEE.-
dc.languageeng-
dc.publisherIEEE. The Journal's web site is located at http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=6963208-
dc.relation.ispartofInternational Conference on Semantics, Knowledge and Grids (SKG)-
dc.rightsInternational Conference on Semantics, Knowledge and Grids (SKG). Copyright © IEEE.-
dc.rights©2014 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.-
dc.rightsCreative Commons: Attribution 3.0 Hong Kong License-
dc.subjectMany-core-
dc.subjectPower management-
dc.subjectPower modelling-
dc.subjectModel-
dc.titleA power modelling approach for many-core architectures-
dc.typeConference_Paper-
dc.identifier.emailLam, KT: kingtin@hku.hk-
dc.identifier.emailWang, CL: clwang@cs.hku.hk-
dc.identifier.authorityWang, CL=rp00183-
dc.description.naturepostprint-
dc.identifier.doi10.1109/SKG.2014.10-
dc.identifier.scopuseid_2-s2.0-84918530824-
dc.identifier.hkuros251498-
dc.identifier.spage128-
dc.identifier.epage132-
dc.publisher.placeUnited States-
dc.customcontrol.immutablesml 151202-

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