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Article: Latency-aware DVFS for Efficient Power State Transitions on Many-core Architectures

TitleLatency-aware DVFS for Efficient Power State Transitions on Many-core Architectures
Authors
Issue Date2015
PublisherKluwer Academic. The Journal's web site is located at http://springerlink.metapress.com/openurl.asp?genre=journal&issn=0920-8542
Citation
Journal of Supercomputing, 2015, v. 71, p. 2720-2747 How to Cite?
AbstractEnergy efficiency is quickly becoming a first-class design constraint in high-performance computing (HPC). We need more efficient power management solutions to save energy costs and carbon footprint of HPC systems. Dynamic voltage and frequency scaling (DVFS) is a commonly used power management technique for making a trade-off between power consumption and system performance according to the time-varying program behavior. However, prior work on DVFS seldom takes into account the voltage and frequency scaling latencies, which we found to be a crucial factor determining the efficiency of the power management scheme. Frequent power state transitions without latency awareness can make a real impact on the execution performance of applications. The design of multiple voltage domains in some many-core architectures has made the effect of DVFS latencies even more significant. These concerns lead us to propose a new latency-aware DVFS scheme to adjust the optimal power state more accurately. Our main idea is to analyze the latency characteristics in depth and design a novel profile-guided DVFS solution which exploits the varying execution patterns of the parallel program to avoid excessive power state transitions. We implement the solution into a power management library for use by shared-memory parallel applications. Experimental evaluation on the Intel SCC many-core platform shows significant improvement in power efficiency after using our scheme. Compared with a latency-unaware approach, we achieve 24.0 % extra energy saving, 31.3 % more reduction in the energy---delay product and 15.2 % less overhead in execution time in the average case for various benchmarks. Our algorithm is also proved to outperform a prior DVFS approach attempted to mitigate the latency effects.
Persistent Identifierhttp://hdl.handle.net/10722/217760

 

DC FieldValueLanguage
dc.contributor.authorLai, Z-
dc.contributor.authorLam, KT-
dc.contributor.authorWang, CL-
dc.contributor.authorSu, J-
dc.date.accessioned2015-09-18T06:12:25Z-
dc.date.available2015-09-18T06:12:25Z-
dc.date.issued2015-
dc.identifier.citationJournal of Supercomputing, 2015, v. 71, p. 2720-2747-
dc.identifier.urihttp://hdl.handle.net/10722/217760-
dc.description.abstractEnergy efficiency is quickly becoming a first-class design constraint in high-performance computing (HPC). We need more efficient power management solutions to save energy costs and carbon footprint of HPC systems. Dynamic voltage and frequency scaling (DVFS) is a commonly used power management technique for making a trade-off between power consumption and system performance according to the time-varying program behavior. However, prior work on DVFS seldom takes into account the voltage and frequency scaling latencies, which we found to be a crucial factor determining the efficiency of the power management scheme. Frequent power state transitions without latency awareness can make a real impact on the execution performance of applications. The design of multiple voltage domains in some many-core architectures has made the effect of DVFS latencies even more significant. These concerns lead us to propose a new latency-aware DVFS scheme to adjust the optimal power state more accurately. Our main idea is to analyze the latency characteristics in depth and design a novel profile-guided DVFS solution which exploits the varying execution patterns of the parallel program to avoid excessive power state transitions. We implement the solution into a power management library for use by shared-memory parallel applications. Experimental evaluation on the Intel SCC many-core platform shows significant improvement in power efficiency after using our scheme. Compared with a latency-unaware approach, we achieve 24.0 % extra energy saving, 31.3 % more reduction in the energy---delay product and 15.2 % less overhead in execution time in the average case for various benchmarks. Our algorithm is also proved to outperform a prior DVFS approach attempted to mitigate the latency effects.-
dc.languageeng-
dc.publisherKluwer Academic. The Journal's web site is located at http://springerlink.metapress.com/openurl.asp?genre=journal&issn=0920-8542-
dc.relation.ispartofJournal of Supercomputing-
dc.titleLatency-aware DVFS for Efficient Power State Transitions on Many-core Architectures-
dc.typeArticle-
dc.identifier.emailLam, KT: kingtin@HKUCC-COM.hku.hk-
dc.identifier.emailWang, CL: clwang@cs.hku.hk-
dc.identifier.authorityWang, CL=rp00183-
dc.identifier.doi10.1007/s11227-015-1415-y-
dc.identifier.hkuros251504-
dc.identifier.volume71-
dc.identifier.spage2720-
dc.identifier.epage2747-
dc.publisher.placeMA, USA-

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