File Download
There are no files associated with this item.
Supplementary
-
Citations:
- Scopus: 0
- Appears in Collections:
Article: SIM-DSP: A DSP-Enhanced CAD Platform for Signal Integrity Macromodeling and Simulation
Title | SIM-DSP: A DSP-Enhanced CAD Platform for Signal Integrity Macromodeling and Simulation |
---|---|
Authors | |
Keywords | High-speed circuits macromodeling Signal integrity Simulation |
Issue Date | 2014 |
Publisher | Brno University of Technology, Faculty of Electrical Engineering and Communication. The Journal's web site is located at http://dx.doi.org/10.13164/re |
Citation | Radioengineering, 2014, v. 23 n. 4, p. 1109-1120 How to Cite? |
Abstract | Macromodeling-Simulation process for signal integrity verifications has become necessary for the high speed circuit system design. This paper aims to introduce a ``VLSI Signal Integrity Macromodeling and Simulation via Digital Signal Processing Techniques'' framework (known as SIM-DSP framework), which applies digital signal processing techniques to facilitate the SI verification process in the pre-layout design phase. Core identification modules and peripheral (pre-/post-)processing modules have been developed and assembled to form a verification flow. In particular, a single-step discrete cosine transform truncation (DCTT) module has been developed for modeling-simulation process. In DCTT, the response modeling problem is classified as a signal compression problem, wherein the system response can be represented by a truncated set of non-pole-based DCT bases, and error can be analyzed through Parseval's theorem. Practical examples are given to show the applicability of our proposed framework. |
Persistent Identifier | http://hdl.handle.net/10722/215299 |
ISSN | 2023 Impact Factor: 0.5 2023 SCImago Journal Rankings: 0.249 |
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Lei, CU | - |
dc.date.accessioned | 2015-08-21T13:21:09Z | - |
dc.date.available | 2015-08-21T13:21:09Z | - |
dc.date.issued | 2014 | - |
dc.identifier.citation | Radioengineering, 2014, v. 23 n. 4, p. 1109-1120 | - |
dc.identifier.issn | 1210-2512 | - |
dc.identifier.uri | http://hdl.handle.net/10722/215299 | - |
dc.description.abstract | Macromodeling-Simulation process for signal integrity verifications has become necessary for the high speed circuit system design. This paper aims to introduce a ``VLSI Signal Integrity Macromodeling and Simulation via Digital Signal Processing Techniques'' framework (known as SIM-DSP framework), which applies digital signal processing techniques to facilitate the SI verification process in the pre-layout design phase. Core identification modules and peripheral (pre-/post-)processing modules have been developed and assembled to form a verification flow. In particular, a single-step discrete cosine transform truncation (DCTT) module has been developed for modeling-simulation process. In DCTT, the response modeling problem is classified as a signal compression problem, wherein the system response can be represented by a truncated set of non-pole-based DCT bases, and error can be analyzed through Parseval's theorem. Practical examples are given to show the applicability of our proposed framework. | - |
dc.language | eng | - |
dc.publisher | Brno University of Technology, Faculty of Electrical Engineering and Communication. The Journal's web site is located at http://dx.doi.org/10.13164/re | - |
dc.relation.ispartof | Radioengineering | - |
dc.subject | High-speed circuits | - |
dc.subject | macromodeling | - |
dc.subject | Signal integrity | - |
dc.subject | Simulation | - |
dc.title | SIM-DSP: A DSP-Enhanced CAD Platform for Signal Integrity Macromodeling and Simulation | - |
dc.type | Article | - |
dc.identifier.email | Lei, CU: culei@eee.hku.hk | - |
dc.identifier.authority | Lei, CU=rp01908 | - |
dc.identifier.scopus | eid_2-s2.0-84922278166 | - |
dc.identifier.hkuros | 246357 | - |
dc.identifier.volume | 23 | - |
dc.identifier.issue | 4 | - |
dc.identifier.spage | 1109 | - |
dc.identifier.epage | 1120 | - |
dc.publisher.place | Czech Republic | - |
dc.identifier.issnl | 1210-2512 | - |