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Conference Paper: Architecture for dual-mode quadruple precision floating point adder

TitleArchitecture for dual-mode quadruple precision floating point adder
Authors
KeywordsFloating point addition
Configurable architecture
Dual-mode arithmetic
ASIC
Digital arithmetic
Issue Date2015
PublisherIEEE Computer Society. The Journal's web site is located at http://ieeexplore.ieee.org/servlet/opac?punumber=1000807
Citation
The 2015 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Montpellier, France, 8-10 July 2015. In Conference Proceedings, 2015, p. 249-254 How to Cite?
AbstractThis paper presents a configurable dual-mode architecture for floating point (F.P.) adder. The architecture (named as QPdDP) works in dual-mode which can operates either for quadruple precision or dual (two-parallel) double precision. The architecture follows the standard state-of-the-art flow for floating point adder. It is aimed for the computation of normal as well as sub-normal operands, along with the support for the exceptional case handling. The key sub-components in the architecture are re-designed & optimized for on-the-fly dual-mode processing, which enables efficient resource sharing for dual precision operands. The data-path is optimized for minimal multiplexing circuitry overhead. The presented dual- mode architecture provide SIMD support for double precision operands, along with high (quadruple) precision support. The proposed architecture is synthesized using UMC 90nm technology ASIC implementation. It is compared with the best available literature works, and have shown better design metrics in terms of area, period and area × period, along with more computational support.
Persistent Identifierhttp://hdl.handle.net/10722/214074
ISBN

 

DC FieldValueLanguage
dc.contributor.authorJaiswal, MK-
dc.contributor.authorBogaraju, SV-
dc.contributor.authorSo, HKH-
dc.date.accessioned2015-08-20T01:07:50Z-
dc.date.available2015-08-20T01:07:50Z-
dc.date.issued2015-
dc.identifier.citationThe 2015 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Montpellier, France, 8-10 July 2015. In Conference Proceedings, 2015, p. 249-254-
dc.identifier.isbn978-1-4799-8719-1-
dc.identifier.urihttp://hdl.handle.net/10722/214074-
dc.description.abstractThis paper presents a configurable dual-mode architecture for floating point (F.P.) adder. The architecture (named as QPdDP) works in dual-mode which can operates either for quadruple precision or dual (two-parallel) double precision. The architecture follows the standard state-of-the-art flow for floating point adder. It is aimed for the computation of normal as well as sub-normal operands, along with the support for the exceptional case handling. The key sub-components in the architecture are re-designed & optimized for on-the-fly dual-mode processing, which enables efficient resource sharing for dual precision operands. The data-path is optimized for minimal multiplexing circuitry overhead. The presented dual- mode architecture provide SIMD support for double precision operands, along with high (quadruple) precision support. The proposed architecture is synthesized using UMC 90nm technology ASIC implementation. It is compared with the best available literature works, and have shown better design metrics in terms of area, period and area × period, along with more computational support.-
dc.languageeng-
dc.publisherIEEE Computer Society. The Journal's web site is located at http://ieeexplore.ieee.org/servlet/opac?punumber=1000807-
dc.relation.ispartofIEEE Computer Society Annual Symposium on VLSI-
dc.rightsIEEE Computer Society Annual Symposium on VLSI. Copyright © IEEE Computer Society.-
dc.rights©2015 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.-
dc.rightsCreative Commons: Attribution 3.0 Hong Kong License-
dc.subjectFloating point addition-
dc.subjectConfigurable architecture-
dc.subjectDual-mode arithmetic-
dc.subjectASIC-
dc.subjectDigital arithmetic-
dc.titleArchitecture for dual-mode quadruple precision floating point adder-
dc.typeConference_Paper-
dc.identifier.emailJaiswal, MK: manishkj@hku.hk-
dc.identifier.emailBogaraju, SV: varma@hku.hk-
dc.identifier.emailSo, HKH: skhay@hkucc.hku.hk-
dc.identifier.authoritySo, HKH=rp00169-
dc.description.naturepublished_or_final_version-
dc.identifier.doi10.1109/ISVLSI.2015.70-
dc.identifier.hkuros249064-
dc.identifier.spage249-
dc.identifier.epage254-
dc.publisher.placeUnited States-
dc.customcontrol.immutablesml 150820-

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