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Conference Paper: An Efficient Two-level DC Operating Points Finder for Transistor Circuits

TitleAn Efficient Two-level DC Operating Points Finder for Transistor Circuits
Authors
Issue Date2014
PublisherACM.
Citation
The 51st Annual Design Automation Conference on Design Automation Conference (DAC14), San Francisco, USA, 2-5 June 2014. In the Proceedings of the 51st Annual Design Automation Conference on Design Automation Conference, 2014, p. 1-6 How to Cite?
AbstractDC analysis, as a foundation for the simulation of many electronic circuits, is concerned with locating DC operating points. In this paper, a new and efficient algorithm to find all DC operating points is proposed for transistor circuits. The novelty of this DC operating points finder is its two-level simple implementation based on the affine arithmetic preconditioning and interval contraction method. Compared to traditional methods such as homotopy, this finder offers a dramatically faster way of computing all roots, without sacrificing any accuracy. Explicit numerical examples and comparative analysis are given to demonstrate the feasibility and accuracy of the proposed approach.
Persistent Identifierhttp://hdl.handle.net/10722/204079
ISBN

 

DC FieldValueLanguage
dc.contributor.authorDeng, Jen_US
dc.contributor.authorBatselier, Ken_US
dc.contributor.authorZhang, Yen_US
dc.contributor.authorWong, Nen_US
dc.date.accessioned2014-09-19T20:04:40Z-
dc.date.available2014-09-19T20:04:40Z-
dc.date.issued2014en_US
dc.identifier.citationThe 51st Annual Design Automation Conference on Design Automation Conference (DAC14), San Francisco, USA, 2-5 June 2014. In the Proceedings of the 51st Annual Design Automation Conference on Design Automation Conference, 2014, p. 1-6en_US
dc.identifier.isbn9781450327305-
dc.identifier.urihttp://hdl.handle.net/10722/204079-
dc.description.abstractDC analysis, as a foundation for the simulation of many electronic circuits, is concerned with locating DC operating points. In this paper, a new and efficient algorithm to find all DC operating points is proposed for transistor circuits. The novelty of this DC operating points finder is its two-level simple implementation based on the affine arithmetic preconditioning and interval contraction method. Compared to traditional methods such as homotopy, this finder offers a dramatically faster way of computing all roots, without sacrificing any accuracy. Explicit numerical examples and comparative analysis are given to demonstrate the feasibility and accuracy of the proposed approach.-
dc.languageengen_US
dc.publisherACM.en_US
dc.relation.ispartofProceedings of the 51st Annual Design Automation Conference on Design Automation Conferenceen_US
dc.titleAn Efficient Two-level DC Operating Points Finder for Transistor Circuitsen_US
dc.typeConference_Paperen_US
dc.identifier.emailBatselier, K: kbatseli@hku.hken_US
dc.identifier.emailZhang, Y: yangzh@hku.hken_US
dc.identifier.emailWong, N: nwong@eee.hku.hken_US
dc.identifier.authorityWong, N=rp00190en_US
dc.identifier.doi10.1145/2593069.2593087-
dc.identifier.hkuros238585en_US
dc.identifier.hkuros236712-
dc.identifier.spage1en_US
dc.identifier.epage6en_US
dc.publisher.placeNew York-

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