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Conference Paper: Mixed-architecture process scheduling on tightly coupled reconfigurable computers
Title | Mixed-architecture process scheduling on tightly coupled reconfigurable computers |
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Authors | |
Issue Date | 2014 |
Citation | The 23rd International Conference on Field Programmable Logic and Applications (FPL 2013), Porto, Portugal, 2-4 September 2013. How to Cite? |
Abstract | The design and implementation of a multitasking runtime system for mixed-architecture applications on a tightly coupled FPGA-CPU platform is presented. The runtime environment and the user applications assume an underlying machine that encompasses multiple computing architectures within a unified machine model. Using this model, a unified process scheduling mechanism was developed that enables concurrent execution of multiple mixed-architecture processes. Scheduling and allocation strategies, including blocking and preemption, were implemented and evaluated with respect to performance and fairness on a Xilinx Zynq platform using a mix of synthetic workloads. |
Persistent Identifier | http://hdl.handle.net/10722/204053 |
DC Field | Value | Language |
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dc.contributor.author | Hamilton, BK | en_US |
dc.contributor.author | Inggs, M | en_US |
dc.contributor.author | So, HKH | en_US |
dc.date.accessioned | 2014-09-19T20:02:07Z | - |
dc.date.available | 2014-09-19T20:02:07Z | - |
dc.date.issued | 2014 | en_US |
dc.identifier.citation | The 23rd International Conference on Field Programmable Logic and Applications (FPL 2013), Porto, Portugal, 2-4 September 2013. | en_US |
dc.identifier.uri | http://hdl.handle.net/10722/204053 | - |
dc.description.abstract | The design and implementation of a multitasking runtime system for mixed-architecture applications on a tightly coupled FPGA-CPU platform is presented. The runtime environment and the user applications assume an underlying machine that encompasses multiple computing architectures within a unified machine model. Using this model, a unified process scheduling mechanism was developed that enables concurrent execution of multiple mixed-architecture processes. Scheduling and allocation strategies, including blocking and preemption, were implemented and evaluated with respect to performance and fairness on a Xilinx Zynq platform using a mix of synthetic workloads. | - |
dc.language | eng | en_US |
dc.relation.ispartof | 23rd International Conference on Field Programmable Logic and Applications Proceedings 2013 | en_US |
dc.title | Mixed-architecture process scheduling on tightly coupled reconfigurable computers | en_US |
dc.type | Conference_Paper | en_US |
dc.identifier.email | So, HKH: skhay@hkucc.hku.hk | en_US |
dc.identifier.authority | So, HKH=rp00169 | en_US |
dc.description.nature | postprint | - |
dc.identifier.hkuros | 236901 | en_US |