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Conference Paper: Mixed-architecture process scheduling on tightly coupled reconfigurable computers

TitleMixed-architecture process scheduling on tightly coupled reconfigurable computers
Authors
Issue Date2014
Citation
The 23rd International Conference on Field Programmable Logic and Applications (FPL 2013), Porto, Portugal, 2-4 September 2013. How to Cite?
AbstractThe design and implementation of a multitasking runtime system for mixed-architecture applications on a tightly coupled FPGA-CPU platform is presented. The runtime environment and the user applications assume an underlying machine that encompasses multiple computing architectures within a unified machine model. Using this model, a unified process scheduling mechanism was developed that enables concurrent execution of multiple mixed-architecture processes. Scheduling and allocation strategies, including blocking and preemption, were implemented and evaluated with respect to performance and fairness on a Xilinx Zynq platform using a mix of synthetic workloads.
Persistent Identifierhttp://hdl.handle.net/10722/204053

 

DC FieldValueLanguage
dc.contributor.authorHamilton, BKen_US
dc.contributor.authorInggs, Men_US
dc.contributor.authorSo, HKHen_US
dc.date.accessioned2014-09-19T20:02:07Z-
dc.date.available2014-09-19T20:02:07Z-
dc.date.issued2014en_US
dc.identifier.citationThe 23rd International Conference on Field Programmable Logic and Applications (FPL 2013), Porto, Portugal, 2-4 September 2013.en_US
dc.identifier.urihttp://hdl.handle.net/10722/204053-
dc.description.abstractThe design and implementation of a multitasking runtime system for mixed-architecture applications on a tightly coupled FPGA-CPU platform is presented. The runtime environment and the user applications assume an underlying machine that encompasses multiple computing architectures within a unified machine model. Using this model, a unified process scheduling mechanism was developed that enables concurrent execution of multiple mixed-architecture processes. Scheduling and allocation strategies, including blocking and preemption, were implemented and evaluated with respect to performance and fairness on a Xilinx Zynq platform using a mix of synthetic workloads.-
dc.languageengen_US
dc.relation.ispartof23rd International Conference on Field Programmable Logic and Applications Proceedings 2013en_US
dc.rightsCreative Commons: Attribution 3.0 Hong Kong License-
dc.titleMixed-architecture process scheduling on tightly coupled reconfigurable computersen_US
dc.typeConference_Paperen_US
dc.identifier.emailSo, HKH: skhay@hkucc.hku.hken_US
dc.identifier.authoritySo, HKH=rp00169en_US
dc.description.naturepostprint-
dc.identifier.hkuros236901en_US

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