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Conference Paper: Fast Transistor-Level Circuit Simulation and Variational Analysis via the Ultra-Compact Virtual Source Model

TitleFast Transistor-Level Circuit Simulation and Variational Analysis via the Ultra-Compact Virtual Source Model
Authors
Issue Date2013
PublisherI E E E. The Journal's web site is located at http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=6805351
Citation
The IEEE 10th International Conference on ASIC (ASICON), Shenzhen, China, 28-31 October 2013. In IEEE International Conference on ASIC Proceedings, 2013, p. 1-4 How to Cite?
AbstractVirtual source (VS) transistor model surpasses the existing threshold-voltage-based and surface-potential-based models in terms of compactness, featuring an order of magnitude fewer parameters while maintaining the same accuracy. This brings about significant simulation speedup and improved ease in variational analyses. This paper demonstrates, for the first time, the quadratic linearization of a VS model into an equivalent state-space form of nonlinear differential algebraic equations. Such transformation allows fast transistor-level analog circuit simulation utilizing nonlinear model order reduction (NMOR) techniques. Moreover, device-to-system-level variational analysis is largely facilitated via the integration of parameterized NMOR and stochastic spectral collocation methods. Experimental results then verify the efficacy of the proposed macromodeling approach.
DescriptionInvited Special Session Paper
Persistent Identifierhttp://hdl.handle.net/10722/204033
ISBN

 

DC FieldValueLanguage
dc.contributor.authorZhang, Yen_US
dc.contributor.authorChen, Qen_US
dc.contributor.authorWong, Nen_US
dc.date.accessioned2014-09-19T20:01:42Z-
dc.date.available2014-09-19T20:01:42Z-
dc.date.issued2013en_US
dc.identifier.citationThe IEEE 10th International Conference on ASIC (ASICON), Shenzhen, China, 28-31 October 2013. In IEEE International Conference on ASIC Proceedings, 2013, p. 1-4en_US
dc.identifier.isbn9781467364157-
dc.identifier.urihttp://hdl.handle.net/10722/204033-
dc.descriptionInvited Special Session Paper-
dc.description.abstractVirtual source (VS) transistor model surpasses the existing threshold-voltage-based and surface-potential-based models in terms of compactness, featuring an order of magnitude fewer parameters while maintaining the same accuracy. This brings about significant simulation speedup and improved ease in variational analyses. This paper demonstrates, for the first time, the quadratic linearization of a VS model into an equivalent state-space form of nonlinear differential algebraic equations. Such transformation allows fast transistor-level analog circuit simulation utilizing nonlinear model order reduction (NMOR) techniques. Moreover, device-to-system-level variational analysis is largely facilitated via the integration of parameterized NMOR and stochastic spectral collocation methods. Experimental results then verify the efficacy of the proposed macromodeling approach.-
dc.languageengen_US
dc.publisherI E E E. The Journal's web site is located at http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=6805351-
dc.relation.ispartofIEEE International Conference on ASIC Proceedingsen_US
dc.rightsIEEE International Conference on ASIC Proceedings. Copyright © I E E E.-
dc.rights©2013 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.-
dc.rightsCreative Commons: Attribution 3.0 Hong Kong License-
dc.titleFast Transistor-Level Circuit Simulation and Variational Analysis via the Ultra-Compact Virtual Source Modelen_US
dc.typeConference_Paperen_US
dc.identifier.emailChen, Q: q1chen@hku.hken_US
dc.identifier.emailWong, N: nwong@eee.hku.hken_US
dc.identifier.authorityChen, Q=rp01688en_US
dc.identifier.authorityWong, N=rp00190en_US
dc.description.naturepublished_or_final_version-
dc.identifier.doi10.1109/ASICON.2013.6811856-
dc.identifier.scopuseid_2-s2.0-84901371220-
dc.identifier.hkuros236710en_US
dc.identifier.spage1en_US
dc.identifier.epage4en_US
dc.publisher.placeUnited States-

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