Fast Transistor-Level Circuit Simulation and Variational Analysis via the Ultra-Compact Virtual Source Model

Abstract

Virtual source (VS) transistor model surpasses the existing threshold-voltage-based and surface-potential-based models in terms of compactness, featuring an order of magnitude fewer parameters while maintaining the same accuracy. This brings about significant simulation speedup and improved ease in variational analyses. This paper demonstrates, for the first time, the quadratic linearization of a VS model into an equivalent state-space form of nonlinear differential algebraic equations. Such transformation allows fast transistor-level analog circuit simulation utilizing nonlinear model order reduction (NMOR) techniques. Moreover, device-to-system-level variational analysis is largely facilitated via the integration of parameterized NMOR and stochastic spectral collocation methods. Experimental results then verify the efficacy of the proposed macromodeling approach.