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Conference Paper: Rhymes: a shared virtual memory system for non-coherent tiled many-core architectures

TitleRhymes: a shared virtual memory system for non-coherent tiled many-core architectures
Authors
KeywordsCache coherence
Software managed coherence
Non-coherent many-core architectures
Issue Date2014
PublisherInstitute of Electrical and Electronics Engineers. The Journal's web site is located at http://ieeexplore.ieee.org/xpl/conhome.jsp?punumber=1000534
Citation
The 20th IEEE International Conference on Parallel and Distributed Systems (ICPADS 2014), Hsinchu, Taiwan, 16-19 December 2014. In International Conference on Parallel and Distributed Systems Proceedings, 2014, p. 1-8 How to Cite?
AbstractThe rising core count per processor is pushing chip complexity to a level that hardware-based cache coherency protocols become too hard and costly to scale. We need new designs of many-core hardware and software other than traditional technologies to keep up with the ever-increasing scalability demands. The Intel Single-chip Cloud Computer (SCC) is a recent research processor exemplifying a new cluster-on-chip architecture which promotes a software-oriented approach instead of hardware support to implementing shared memory coherence. This paper presents a shared virtual memory (SVM) system, dubbed Rhymes, tailored to such a new processor kind of non-coherent and hybrid memory architectures. Rhymes features a two-way cache coherence protocol to enforce release consistency for pages allocated in shared physical memory (SPM) and scope consistency for pages in per-core private memory. It also supports page remapping on a per-core basis to boost data locality. We implement Rhymes on the SCC port of the Barrelfish OS. Experimental results show that our SVM outperforms the pure SPM approach used by Intel's software managed coherence (SMC) library by up to 12 times, with superlinear speedups (due to L2 cache effect) noted for applications with strong data reuse patterns.
Persistent Identifierhttp://hdl.handle.net/10722/203645
ISSN

 

DC FieldValueLanguage
dc.contributor.authorLam, KTen_US
dc.contributor.authorShi, Jen_US
dc.contributor.authorHung, DCHen_US
dc.contributor.authorWang, CL-
dc.contributor.authorLai, Z-
dc.contributor.authorZhu, W-
dc.contributor.authorYan, Y-
dc.date.accessioned2014-09-19T15:49:09Z-
dc.date.available2014-09-19T15:49:09Z-
dc.date.issued2014en_US
dc.identifier.citationThe 20th IEEE International Conference on Parallel and Distributed Systems (ICPADS 2014), Hsinchu, Taiwan, 16-19 December 2014. In International Conference on Parallel and Distributed Systems Proceedings, 2014, p. 1-8en_US
dc.identifier.issn1521-9097-
dc.identifier.urihttp://hdl.handle.net/10722/203645-
dc.description.abstractThe rising core count per processor is pushing chip complexity to a level that hardware-based cache coherency protocols become too hard and costly to scale. We need new designs of many-core hardware and software other than traditional technologies to keep up with the ever-increasing scalability demands. The Intel Single-chip Cloud Computer (SCC) is a recent research processor exemplifying a new cluster-on-chip architecture which promotes a software-oriented approach instead of hardware support to implementing shared memory coherence. This paper presents a shared virtual memory (SVM) system, dubbed Rhymes, tailored to such a new processor kind of non-coherent and hybrid memory architectures. Rhymes features a two-way cache coherence protocol to enforce release consistency for pages allocated in shared physical memory (SPM) and scope consistency for pages in per-core private memory. It also supports page remapping on a per-core basis to boost data locality. We implement Rhymes on the SCC port of the Barrelfish OS. Experimental results show that our SVM outperforms the pure SPM approach used by Intel's software managed coherence (SMC) library by up to 12 times, with superlinear speedups (due to L2 cache effect) noted for applications with strong data reuse patterns.en_US
dc.languageengen_US
dc.publisherInstitute of Electrical and Electronics Engineers. The Journal's web site is located at http://ieeexplore.ieee.org/xpl/conhome.jsp?punumber=1000534en_US
dc.relation.ispartofInternational Conference on Parallel and Distributed Systems Proceedingsen_US
dc.rights©2014 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.en_US
dc.rightsCreative Commons: Attribution 3.0 Hong Kong Licenseen_US
dc.subjectCache coherence-
dc.subjectSoftware managed coherence-
dc.subjectNon-coherent many-core architectures-
dc.titleRhymes: a shared virtual memory system for non-coherent tiled many-core architecturesen_US
dc.typeConference_Paperen_US
dc.identifier.emailLam, KT: kingtin@hku.hken_US
dc.identifier.emailWang, CL: clwang@cs.hku.hken_US
dc.identifier.authorityWang, CL=rp00183en_US
dc.description.naturepublished_or_final_version-
dc.identifier.hkuros239050en_US
dc.identifier.spage1-
dc.identifier.epage8-
dc.publisher.placeUnited States-
dc.customcontrol.immutablesml 141120-

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