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Conference Paper: Map-reduce processing of K-means algorithm with FPGA-accelerated computer cluster

TitleMap-reduce processing of K-means algorithm with FPGA-accelerated computer cluster
Authors
Issue Date2014
PublisherIEEE. The Journal's web site is located at http://ieeexplore.ieee.org/xpl/conhome.jsp?punumber=1000037
Citation
The 25th IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP 2014), Zurich, Switzerland, 18-20 June 2014. In Conference Proceedings, 2014, p. 9-16 How to Cite?
AbstractThe design and implementation of the k-means clustering algorithm on an FPGA-accelerated computer cluster is presented. The implementation followed the map-reduce programming model, with both the map and reduce functions executing autonomously to the CPU on multiple FPGAs. A hardware/software framework was developed to manage gateware execution on multiple FPGAs across the cluster. Using this k-means implementation as an example, system-level tradeoff study between computation and I/O performance in the target multi-FPGA execution environment was performed. When compared to a similar software implementation executing over the Hadoop MapReduce framework, 15.5× to 20.6× performance improvement has been achieved across a range of input data sets.
Persistent Identifierhttp://hdl.handle.net/10722/201236
ISBN

 

DC FieldValueLanguage
dc.contributor.authorChoi, YMen_US
dc.contributor.authorSo, HKHen_US
dc.date.accessioned2014-08-21T07:18:19Z-
dc.date.available2014-08-21T07:18:19Z-
dc.date.issued2014en_US
dc.identifier.citationThe 25th IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP 2014), Zurich, Switzerland, 18-20 June 2014. In Conference Proceedings, 2014, p. 9-16en_US
dc.identifier.isbn978-1-4799-3609-0-
dc.identifier.urihttp://hdl.handle.net/10722/201236-
dc.description.abstractThe design and implementation of the k-means clustering algorithm on an FPGA-accelerated computer cluster is presented. The implementation followed the map-reduce programming model, with both the map and reduce functions executing autonomously to the CPU on multiple FPGAs. A hardware/software framework was developed to manage gateware execution on multiple FPGAs across the cluster. Using this k-means implementation as an example, system-level tradeoff study between computation and I/O performance in the target multi-FPGA execution environment was performed. When compared to a similar software implementation executing over the Hadoop MapReduce framework, 15.5× to 20.6× performance improvement has been achieved across a range of input data sets.en_US
dc.languageengen_US
dc.publisherIEEE. The Journal's web site is located at http://ieeexplore.ieee.org/xpl/conhome.jsp?punumber=1000037en_US
dc.relation.ispartofInternational Conference on Application Specific Systems (ASAP), Architectures and Processors Proceedingsen_US
dc.rightsInternational Conference on Application Specific Systems (ASAP), Architectures and Processors Proceedings. Copyright © IEEE.en_US
dc.rights©2014 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.en_US
dc.rightsCreative Commons: Attribution 3.0 Hong Kong License-
dc.titleMap-reduce processing of K-means algorithm with FPGA-accelerated computer clusteren_US
dc.typeConference_Paperen_US
dc.identifier.emailSo, HKH: skhay@hkucc.hku.hken_US
dc.identifier.authoritySo, HKH=rp00169en_US
dc.description.naturepublished_or_final_version-
dc.identifier.doi10.1109/ASAP.2014.6868624en_US
dc.identifier.hkuros234178en_US
dc.identifier.spage9en_US
dc.identifier.epage16en_US
dc.publisher.placeUnited States-
dc.customcontrol.immutablesml 140822-

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