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Conference Paper: A concurrent error detection based fault-tolerant 32 nm XOR-XNOR circuit implementation

TitleA concurrent error detection based fault-tolerant 32 nm XOR-XNOR circuit implementation
Authors
KeywordsXOR-XNOR circuit
Transistor stuck-open fault model
Transistor stuck-on fault model
Stuck-at fault model
Fault-tolerant systems
Concurrent Error Detection (CED)
Issue Date2012
Citation
International MultiConference of Engineers and Computer Scientists (IMECS), Hong Kong, China, 14-16 March 2012. In Lecture Notes in Engineering and Computer Science, 2012, v. 2, p. 1177-1180 How to Cite?
AbstractAs modern processors and semiconductor circuits move into 32 nm technologies and below, designers face the major problem of process variations. This problem makes designing VLSI circuits harder and harder, affects the circuit performance and introduces faults that can cause critical failures. Therefore, fault-tolerant design is required to obtain the necessary level of reliability and availability especially for safety-critical systems. Since XOR-XNOR circuits are basic building blocks in various digital and mixed systems, especially in arithmetic circuits, these gates should be designed such that they indicate any malfunction during normal operation. In fact, this property of verifying the results delivered by a circuit during its normal operation is called Concurrent Error Detection (CED). In this paper, we propose a CED based fault- tolerant XOR-XNOR circuit implementation. The proposed design is performed using the 32 nm process technology.
Persistent Identifierhttp://hdl.handle.net/10722/198903
ISBN
ISSN

 

DC FieldValueLanguage
dc.contributor.authorKarmani, Mouna-
dc.contributor.authorKhedhiri, Chiraz-
dc.contributor.authorHamdi, Belgacem-
dc.contributor.authorMan, K. L.-
dc.contributor.authorLim, Enggee-
dc.contributor.authorLei, Chi-Un-
dc.date.accessioned2014-07-17T03:52:28Z-
dc.date.available2014-07-17T03:52:28Z-
dc.date.issued2012-
dc.identifier.citationInternational MultiConference of Engineers and Computer Scientists (IMECS), Hong Kong, China, 14-16 March 2012. In Lecture Notes in Engineering and Computer Science, 2012, v. 2, p. 1177-1180-
dc.identifier.isbn9789881925190-
dc.identifier.issn2078-0958-
dc.identifier.urihttp://hdl.handle.net/10722/198903-
dc.description.abstractAs modern processors and semiconductor circuits move into 32 nm technologies and below, designers face the major problem of process variations. This problem makes designing VLSI circuits harder and harder, affects the circuit performance and introduces faults that can cause critical failures. Therefore, fault-tolerant design is required to obtain the necessary level of reliability and availability especially for safety-critical systems. Since XOR-XNOR circuits are basic building blocks in various digital and mixed systems, especially in arithmetic circuits, these gates should be designed such that they indicate any malfunction during normal operation. In fact, this property of verifying the results delivered by a circuit during its normal operation is called Concurrent Error Detection (CED). In this paper, we propose a CED based fault- tolerant XOR-XNOR circuit implementation. The proposed design is performed using the 32 nm process technology.-
dc.languageeng-
dc.relation.ispartofLecture Notes in Engineering and Computer Science-
dc.rightsCreative Commons: Attribution 3.0 Hong Kong License-
dc.subjectXOR-XNOR circuit-
dc.subjectTransistor stuck-open fault model-
dc.subjectTransistor stuck-on fault model-
dc.subjectStuck-at fault model-
dc.subjectFault-tolerant systems-
dc.subjectConcurrent Error Detection (CED)-
dc.titleA concurrent error detection based fault-tolerant 32 nm XOR-XNOR circuit implementation-
dc.typeConference_Paper-
dc.description.naturepublished_or_final_version-
dc.identifier.scopuseid_2-s2.0-84867459088-
dc.identifier.hkuros230679-
dc.identifier.volume2-
dc.identifier.spage1177-
dc.identifier.epage1180-

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